Sam Kavusi

Resolution and light sensitivity tradeoff with pixel size

When the size of a CMOS imaging sensor array is fixed, the only way to increase sampling density and spatial resolution is to reduce pixel size. But reducing pixel size reduces the light sensitivity. Hence, under these constraints, there is a tradeoff between spatial resolution and light sensitivity. Because this tradeoff involves the interaction of many different system components, we used a full system simulation to characterize performance. This paper describes system simulations that predict the output of imaging sensors with the same dye size but different pixel sizes and presents metrics that quantify the spatial resolution and light sensitivity for these different imaging sensors.

Computationally efficient algorithm for multifocus image reconstruction

A method for synthesizing enhanced depth of field digital still camera pictures using multiple differently focused images is presented. This technique exploits only spatial image gradients in the initial decision process. The image gradient as a focus measure has been shown to be experimentally valid and theoretically sound under weak assumptions with respect to unimodality and monotonicity. Subsequent majority filtering corroborates decisions with those of neighboring pixels, while the use of soft decisions enables smooth transitions across region boundaries. Furthermore, these last two steps add algorithmic robustness for coping with both sensor noise and optics-related effects, such as misregistration or optical flow, and minor intensity fluctuations. The dependence of these optical effects on several optical parameters is analyzed and potential remedies that can allay their impact with regard to the techniques limitations are discussed. Several examples of image synthesis using the algorithm are presented. Finally, leveraging the increasing functionality and emerging processing capabilities of digital still cameras, the method is shown to entail modest hardware requirements and is implementable using a parallel or general purpose processor.

On incremental sigma-delta modulation with optimal filtering

The paper presents a quantization-theoretic framework for studying incremental sigma-delta (/spl Sigma//spl Delta/) data conversion systems. The framework makes it possible to efficiently compute the quantization intervals and hence the transfer function of the quantizer, and to determine the mean square error (MSE) and maximum error for the optimal and conventional linear filters for first and second order incremental /spl Sigma//spl Delta/ modulators. The results show that the optimal filter can significantly outperform conventional linear filters in terms of both MSE and maximum error. The performance of conventional /spl Sigma//spl Delta/ data converters is then compared to that of incremental /spl Sigma//spl Delta/ with optimal filtering for bandlimited signals. It is shown that incremental /spl Sigma//spl Delta/ can outperform the conventional approach in terms of signal-to-noise-and-distortion ratio. The framework is also used to provide a simpler and more intuitive derivation of the Zoomer algorithm.

Quantitative study of high-dynamic-range image sensor architectures

Analysis of dynamic-range (DR) and signal-to-noise-ratio (SNR) for high fidelity, high-dynamic-range (HDR) image sensor architectures is presented. Four architectures are considered: (i) time-to-saturation, (ii) multiple-capture, (iii) asynchronous self-reset with multiple capture, and (iv) synchronous self-reset with residue readout. The analysis takes into account circuit nonidealities such as quantization noise and the effects of limited pixel area on building block and reference signal performance and accuracy. Examples that demonstrate the behavior of SNR in the extended DR and implementation and power consumption issues for each scheme are presented.

Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits

The stringent performance requirements of many infrared imaging applications warrant the development of precision high dynamic range, high speed focal plane arrays. In addition to achieving high dynamic range, the readout circuits for these image sensors must achieve high linearity and SNR at low power consumption. Two high dynamic range image sensor schemes that have been developed for visible range imaging were reviewed first and discuss why they cannot meet the stringent performance demands of infrared imaging. A new dynamic range extension scheme, folded multiple capture, was then described that can meet these performance requirements. Dynamic range is extended using synchronous self-reset while high SNR is maintained using few non-uniformly spaced captures and least-squares fit to estimate pixel photocurrent. The paper concludes with a description of a prototype of this architecture targeted for 3D-IC IR focal plane arrays

Folded multiple-capture: an architecture for high dynamic range disturbance-tolerant focal plane array

Earlier studies have shown that multiple capture can achieve high SNR, but cannot satisfy the high dynamic range (HDR) and high speed requirements of the Vertically-Integrated-Sensor-Array (VISA) project. Synchronous self-reset, on the other hand, can achieve these requirements, but suffers from poor SNR. Extended counting can achieve high dynamic range at high frame rate and with good SNR, but at the expense of high power consumption. The paper proposes a new HDR focal plane array architecture, denoted by folded-multiple capture (FMC), which by combining features of the synchronous self-reset and multiple capture schemes, can satisfy the VISA requirements at a fraction of the power dissipation and with more robustness to device variations than extended counting. The architecture is also capable of detecting subframe disturbances, e.g., due to laser jamming, and correcting for it.

A Per-Pixel Pulse-FM Background Subtraction Circuit with 175ppm Accuracy for Imaging Applications

A per-pixel background subtraction circuit for infrared and fluorescence imaging applications is presented. Charge packets controlled by a pulse-FM signal are subtracted from the integrator of each pixel. A 1times16 array of 30mum pixels prototyped in a 0.18mum CMOS process achieves noise, linearity, and spatial current variation of 175ppm, 270ppm, and 3%, respectively, at 43fps

A 0.18μm CMOS 1000 frames/sec, 138dB Dynamic Range Readout Circuit for 3D-IC IR Focal Plane Arrays

A prototype of a new high dynamic range readout scheme targeted for 3D-IC IR focal plane arrays is described. Dynamic range is extended using synchronous self-reset while high SNR is maintained using few non-uniformly spaced captures and least-squares fit to estimate pixel photocurrent. The prototype comprises of a 16times5 readout pixel array fabricated in a 0.18μmum CMOS process and achieves 138dB dynamic range and 60dB peak SNR at 1000 frames/sec with energy consumption of 25.5nJ per pixel readout.