Sameh G. Khalil

Normally-off GaN-on-Si multi-chip module boost converter with 96% efficiency and low gate and drain overshoot

A high efficiency synchronous GaN half-bridge boost converter with fast switching and low overshoot is achieved by minimizing parasitic inductance and critical damping the gate drive. A normally-off GaN-on-Si 2.4kW synchronous halfbridge Multi-Chip Module (MCM) is designed with a power-loop inductance of ~4nH using transmission-line techniques to minimize inductance. The gate circuit inductance is reduced to 1nH using bare MOSFET die for driving the GaN gates and a 0.5mil flexible substrate gate transmission-line. Configured as a boost converter with no added gate resistance, the synchronous half-bridge switches 400V in only 1.3ns. The high voltage slew rates of 325V/ns results in overshoot of 200V on the drain and 4V overshoot on the gate, both of which may damage the GaN switches. Critically damping the gate turn-on reduces overshoot to safe levels of 1V gate overshoot and ~20V drain overshoot. The gate damping increases drain fall time to 3ns, which only decreases efficiency by 0.2% at 1MHz. The resulting synchronous boost converter has an efficiency of 96%, switching 300V at 1MHz with 50% duty cycle and an output power of 2.4kW. The high efficiency of GaN switches and the 0.6C/W thermal resistance of the MCM enable a maximum junction temperature of 65°C.

Normally-Off GaN-on-Si transistors enabling nanosecond power switching at one kilowatt

Power switches based on GaN-on-Si transistor technology have the advantage of high switching speed and low fabrication cost. This paper reports our recent advancement in device technology which enabled nanosecond switching at one kilowatt, with an unprecedented slew rate of 325 V/ns. The high switching speed opens up pathways for emerging applications such as envelope tracking and wireless power charging.

Normally-off gate-recessed AlGaN/GaN-on-Si hybrid MOS-HFET with Al 2 O 3 gate dielectric

GaN-based HFETs offer a combination of high breakdown field, high current densities, and low on-resistance, making them well-suited for power-switching applications. Normally-off FETs are preferred in power switching applications for circuit simplicity and safety. Recently, a new type of normally-off GaN device has been reported: the hybrid metal-oxide-semiconductor (MOS)- or metal-insulator-semiconductor (MIS)-HFET, consisting of an MOS-type structure under the gate for normally-off operation and an HFET-like structure in the access regions for low on-resistance [1–6]. Optimization of the insulator-epi interface and insulator quality is critical for this type of device, since the electrons under gate electrode are in direct contact with the gate insulator. Previous reports of hybrid MOS-HFETs used SiO2 or SiN gate dielectrics deposited by plasma-enhanced chemical vapor deposition (PECVD). However, alternative deposition methods such as atomic layer deposition (ALD) have been shown to result in superior thickness control, uniformity, conformality, and film quality, while ALD high-k gate dielectrics such as Al2O3 have generated significant interest for GaN HFETs due to excellent GaN interface quality. In this work, we fabricated normally-off AlGaN/GaN hybrid MOS-HFETs on (111) Si substrates using gate recess etching combined with an ALD Al2O3 gate dielectric for low gate leakage, low on-resistance, and high breakdown voltage. The gate fabrication process was optimized to reduce the trap density associated with the dielectric and eliminate threshold voltage hysteresis, which can result from slow traps in the dielectric or at the dielectric-epi interface [7]. A three-terminal breakdown voltage (VB) of 1370V was measured at a gate bias of 0 V on a device with a 20 mm gate periphery and a low specific on-resistance (Ron) of 9.0 mΩ-cm2. The resulting VB2/Ron figure of merit of 208 MW/cm2 is among the highest values reported to-date for normally-off GaN-on-Si HFETs.

Improvement of the dynamic on-resistance characteristics of GaN-on-Si power transistors with a sloped field-plate

High Electron Mobility Transistors (HEMTs) based on GaN are attractive for high-speed and high-voltage applications. The performance advantages of the GaN HEMTs rely on the high breakdown field of the GaN material and the high electron mobility of the 2-dimesional electron gas (2DEG) in the AlGaN/GaN heterojunction [1, 2]. In order to take full advantage of the excellent material properties, the shape of the electric-field distribution in the GaN HEMTs must be carefully optimized to operate the device at its highest switching speed while handling a large voltage swing. Without proper field-shaping, a high electric-field can cause electron injection into traps, hence degrading the output current and on-resistance during switching operation. This phenomenon is often referred to as dynamic on-resistance (Ron dynamic) degradation, current collapse or DC-RF dispersion. As an effective approach of shaping the electric-field, the use of field-plates in GaN HEMTs has received extensive studies [3]. For microwave applications, a V-shaped gate with integrated sloped field-plate was used to control the electric-field with minimal added capacitance associated with the field-plate [5, 6]. For high-voltage applications, a multiple field-plates structure was used to scale up the operating voltage [2, 4]. In this paper, we report a sloped field-plate approach for high-voltage applications.

Impact of gate stack on the stability of normally-Off AlGaN/GaN power switching HEMTs

We have examined the response of AlGaN/GaN power switching HEMTs to electrical bias stress. Three different gate stack structures were studied. In devices containing a ~ 5 nm thick AlGaN layer in the gate stack, both positive and negative shifts in the threshold voltage were observed following high blocking voltage stress, consistent with a short initial period of electron trapping followed by a longer period of de-trapping. Correlated changes in reverse bias leakage current were also observed, although this also occurred in devices containing only residual AlGaN in the gate stack. The data have been explained by a field-enhanced emission model in which an electron trapping to de-trapping transition occurs. The exact nature of the transition is found to be sensitive to a variety of parameters including trap energy, geometry, and initial and boundary conditions.

Critical gate module process enabling the implementation of a 50A/600V AlGaN/GaN MOS-HEMT

Two critical processes within the gate module of GaN-based MOS-HEMT with significant impact on device robustness and performance were identified and are presented in this paper. Specifically, data highlighting the impact of the number of cycles of the atomic layer etching of the AlGaN barrier to recess the gate region and the sequence of the gate dielectric anneal step on device performance are discussed. The optimization of these two critical steps enabled the implementation of a 50A/600V with an off-state leakage current of 455 μA at 600V and on-state resistance of 41mΩ at VGS=2.5V.

Trap-Related Parametric Shifts under DC Bias and Switched Operation Life Stress in Power AlGaN/GaN HEMTs.

This paper reports on trap-related shifts of the transfer curve and threshold voltage of power AlGaN/GaN HEMTs under switched bias operating life and reverse and forward DC bias stress. Opposite polarity threshold voltage shifts at room temperature under operating life and reverse bias stress conditions can be explained by means of drain current transient measurements under reverse bias stress conditions. A proposed model to explain the trapping/de-trapping behavior under different stress conditions is described and highlights the critical role of the electric field. Experimental evidence of the importance of the role of the electric field is seen in reduced parametric shift by improving the field plate design.