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Featured researches published by Rongming Chu.


IEEE Electron Device Letters | 2011

1200-V Normally Off GaN-on-Si Field-Effect Transistors With Low Dynamic on -Resistance

Rongming Chu; Andrea Corrion; Mary Chen; Ray Li; D. Wong; Daniel Zehnder; Brian Hughes; Karim S. Boutros

This letter reports high-voltage GaN field-effect transistors fabricated on Si substrates. A halide-based plasma treatment was performed to enable normally off operation. Atomic layer deposition of Al2O3 gate insulator was adopted to reduce the gate leakage current. Incorporation of multiple field plates, with one field plate connected to the gate electrode and two field plates connected to the source electrode successfully enabled a high breakdown voltage of 1200 V and low dynamic on-resistance at high-voltage operation.


Applied Physics Letters | 2016

High-voltage vertical GaN Schottky diode enabled by low-carbon metal-organic chemical vapor deposition growth

Yu Cao; Rongming Chu; Ray Li; M. Chen; R. Chang; Brian Hughes

Vertical GaN Schottky barrier diode (SBD) structures were grown by metal-organic chemical vapor deposition on free-standing GaN substrates. The carbon doping effect on SBD performance was studied by adjusting the growth conditions and spanning the carbon doping concentration between ≤3 × 1015 cm−3 and 3 × 1019 cm−3. Using the optimized growth conditions that resulted in the lowest carbon incorporation, a vertical GaN SBD with a 6-μm drift layer was fabricated. A low turn-on voltage of 0.77 V with a breakdown voltage over 800 V was obtained from the device.


IEEE Electron Device Letters | 2016

An Experimental Demonstration of GaN CMOS Technology

Rongming Chu; Yu Cao; Mary Chen; Ray Li; Daniel Zehnder

This letter reports the first demonstration of gallium nitride (GaN) complementary metal-oxide-semi-conductor (CMOS) field-effect-transistor technology. Selective area epitaxy was employed to have both GaN N-channel MOSFET (NMOS) and P-channel MOSFET (PMOS) structures on the same wafer. An AlN/SiN dielectric stack grown by metal-organic chemical vapor deposition served as the gate oxide for both NMOS and PMOS, yielding enhancement-mode N- and P-channel with the electron mobility of 300 cm2/V-s and hole mobility of 20 cm2/V-s, respectively. Using the GaN CMOS technology, a functional inverter integrated circuit was fabricated and characterized.


IEEE Electron Device Letters | 2016

600 V/

Ray Li; Yu Cao; Mary Chen; Rongming Chu

This letter reports a GaN vertical trench metal-oxide-semiconductor field-effect transistor (MOSFET) with normally-off operation. Selective area regrowth of n±GaN source layer was performed to avoid plasma etch damage to the p-GaN body contact region. A metal-organic-chemicalvapor-deposition (MOCVD) grown AlN/SiN dielectric stack was employed as the gate “oxide”. This unique process yielded a 0.5-mm2-active-area transistor with threshold voltage of 4.8 V, blocking voltage of 600 V at gate bias of 0 V, and on-resistance of 1.7 Ω at gate bias of 10 V.


applied power electronics conference | 2014

1.7~\Omega

Brian Hughes; James Lazar; Stephen Hulsey; Marcel Musni; Daniel Zehnder; Austin Garrido; Raghav Khanna; Rongming Chu; Sameh G. Khalil; Karim S. Boutros

A high efficiency synchronous GaN half-bridge boost converter with fast switching and low overshoot is achieved by minimizing parasitic inductance and critical damping the gate drive. A normally-off GaN-on-Si 2.4kW synchronous halfbridge Multi-Chip Module (MCM) is designed with a power-loop inductance of ~4nH using transmission-line techniques to minimize inductance. The gate circuit inductance is reduced to 1nH using bare MOSFET die for driving the GaN gates and a 0.5mil flexible substrate gate transmission-line. Configured as a boost converter with no added gate resistance, the synchronous half-bridge switches 400V in only 1.3ns. The high voltage slew rates of 325V/ns results in overshoot of 200V on the drain and 4V overshoot on the gate, both of which may damage the GaN switches. Critically damping the gate turn-on reduces overshoot to safe levels of 1V gate overshoot and ~20V drain overshoot. The gate damping increases drain fall time to 3ns, which only decreases efficiency by 0.2% at 1MHz. The resulting synchronous boost converter has an efficiency of 96%, switching 300V at 1MHz with 50% duty cycle and an output power of 2.4kW. The high efficiency of GaN switches and the 0.6C/W thermal resistance of the MCM enable a maximum junction temperature of 65°C.


device research conference | 2013

Normally-Off GaN Vertical Trench Metal–Oxide–Semiconductor Field-Effect Transistor

Rongming Chu; Brian Hughes; Mary Chen; David F. Brown; Ray Li; Sameh G. Khalil; Daniel Zehnder; Steve Chen; Adam J. Williams; Austin Garrido; Marcel Musni; Karim S. Boutros

Power switches based on GaN-on-Si transistor technology have the advantage of high switching speed and low fabrication cost. This paper reports our recent advancement in device technology which enabled nanosecond switching at one kilowatt, with an unprecedented slew rate of 325 V/ns. The high switching speed opens up pathways for emerging applications such as envelope tracking and wireless power charging.


international symposium on power semiconductor devices and ic's | 2012

Normally-off GaN-on-Si multi-chip module boost converter with 96% efficiency and low gate and drain overshoot

Rongming Chu; David F. Brown; Daniel Zehnder; Xu Chen; Adam J. Williams; Ray Li; Mary Chen; Scott Newell; Karim S. Boutros

We report a GaN-on-Si metal-insulator-semiconductor field-effect transistor (MISFET) with normally-off operation and 600-V blocking capability at 200 °C temperature. The temperature-dependences of threshold voltage, on-resistance, and leakage characteristics are discussed.


device research conference | 2011

Normally-Off GaN-on-Si transistors enabling nanosecond power switching at one kilowatt

Rongming Chu; Daniel Zehnder; Brian Hughes; Karim S. Boutros

Field-effect transistors based on the low-cost GaN-on-Si platform are promising candidates for highefficiency power switching at high frequencies. We have reported a normally-off GaN-on-Si switch with a blocking voltage of 1200V, and a very low dynamic on-resistance [1]. For future improvement of the GaN-on-Si switching technology, it is important to understand the role of the non-insulating Si-substrate in device characteristics. In this paper, we discuss the static (DC) and dynamic (switching) characteristics of the GaN-on-Si device, focusing on the impact of bias conditions applied on the Si substrate. It was found that state-of-the-art dynamic on-resistance characteristics of the GaN-on-Si switch can be achieved by properly terminating the Si substrate potential.


Applied Physics Letters | 2016

Normally-off GaN-on-Si metal-insulator-semiconductor field-effect transistor with 600-V blocking capability at 200 °C

Yu Cao; Rongming Chu; Ray Li; M. Chen; Adam J. Williams

In a vertical GaN Schottky barrier diode, the free electron concentration n in the 6-μm-thick drift layer was found to greatly impact the diode reverse leakage current, which increased from 2.1 × 10−7 A to 3.9 × 10−4 A as n increased from 7.5 × 1014 cm−3 to 6.3 × 1015 cm−3 at a reverse bias of 100 V. By capping the drift layer with an ultrathin 5-nm graded AlGaN layer, reverse leakage was reduced by more than three orders of magnitude with the same n in the drift layer. We attribute this to the increased Schottky barrier height with the AlGaN at the surface. Meanwhile, the polarization field within the graded AlGaN effectively shortened the depletion depth, which led to the formation of tunneling current at a relatively small forward bias. The turn-on voltage in the vertical Schottky diodes was reduced from 0.77 V to 0.67 V—an advantage in reducing conduction loss in power switching applications.


IEEE Electron Device Letters | 2013

High performance GaN-on-Si power switch: Role of substrate bias in device characteristics

David F. Brown; K. Shinohara; Andrea Corrion; Rongming Chu; Adam J. Williams; Joel C. Wong; Ivan Alvarado-Rodriguez; Robert Grabar; Michael Johnson; C. Butler; Dayward Santos; Shawn D. Burnham; John F. Robinson; Daniel Zehnder; S. Kim; Thomas C. Oh; Miroslav Micovic

We report a novel GaN heterojunction field-effect transistor device that incorporates vertically scaled epilayers, a nanoscale gate with integrated staircase-shaped field plates, and regrown ohmic contacts. This device technology has an unprecedented combination of high breakdown (176 V), low ON-resistance (1.2 Ωmm), enhancement-mode operation (VTH=+0.35 V), and excellent high-frequency performance (fT/fmax=50/120 GHz), which enables new applications as a high-frequency power switch or a microwave power amplifier. The gate design manages the electric field at the drain edge of the gate, which mitigates dynamic ON-resistance degradation.

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