Samet Zihir

A 60 GHz single-chip 256-element wafer-scale phased array with EIRP of 45 dBm using sub-reticle stitching

This paper presents a 60 GHz wafer-scale transmit phased-array with 256-elements spaced λ/2 apart in the x and y directions, and occupying an area of 4.14×4.2 cm2 (1740 mm2). The phased array is built using independent RF, transmission-line and control circuit blocks which are stitched together to form an aggregate chip which is much larger than a standard reticle (22×22 mm2). This method allows for a wafer-scale design and can be extended to any size and any shape (rectangular, hexagonal, etc.) up to the edge of the wafer. The blocks include high-efficiency on-wafer antennas, phased-array channels with 3-bits amplitude and 5-bits phase control together with an amplifier having an output power of +3 dBm at 60 GHz. Also, a highly redundant RF distribution network is synthesized from several stitched blocks for improved yield, and the control blocks have redundant SPI control and power strips, also for improved yield. The 256-element array results in a half-power beamwidth of 6° in the E- and H-planes, a directivity of 29 dB, and scans to +/- 55° in the E- and H-planes with near-ideal patterns and a cross-polarization level of <;-25 dB. The measured EIRP is 45 dBm at 61 GHz and with a 3-dB bandwidth from 58 to 64 GHz. To our knowledge, this is the largest single-chip phased-array ever developed and allows the construction of large-scale (1000+ elements) phased-array systems, either on a single wafer or by assembling several of these chips together.

A 155 GHz 20 Gbit/s QPSK transceiver in 45nm CMOS

This paper presents a 155 GHz 20 Gbit/s quadrature phase-shift-keying (QPSK) transceiver front-end with modulator, demodulator, LO chain and an option for external LO feed. The transceiver can achieve a bit error rate (BER) <; 10-12 for an 19 Gbit/s 231-1 pseudorandom binary sequence data at a received power of -20 dBm. The size of the chip is 2.8×1.4 mm2 and consumes 345 mW with the on-chip LO (290 mW without the on-chip LO). To our knowledge, this is the first demonstration of a single-chip QPSK transceiver in CMOS at frequencies above 100 GHz.

A 60 GHz 64-element wafer-scale phased-array with full-reticle design

This paper presents the first large-scale wafer-scale phased-array at 60 GHz with 64-elements spaced λ/2 apart and occupying a full reticle area of 2.2×2.2 cm2. The transmit array includes high-efficiency on-wafer antennas, 3-bits amplitude and 5-bits phase control on each element, and a highly redundant RF distribution network for improved yield. It also includes redundant SPI control and power strips, also for improved yield. The 64-element array results in a half-power beamwidth of 12.5° in the E- and H-planes, a directivity of 23 dB and scans to +/- 55° in the E- and H-planes with near-ideal patterns and a cross-polarization level of >-25 dB. The measured EIRP is 38 dBm at 66 GHz, but this is currently being redone for improved accuracy. To our knowledge, this is the largest single-chip phased-array ever developed and paves the way to mm-wave large-scale (1000+ elements) phased-array systems.

60-GHz 64- and 256-Elements Wafer-Scale Phased-Array Transmitters Using Full-Reticle and Subreticle Stitching Techniques

This paper presents 60-GHz wafer-scale transmit phased arrays with 64- and 256-elements spaced λ/2 apart in the x- and y-directions, and occupying an area of 21.4 × 22 mm2 (471 mm2) and 41.4 × 42 mm2 (1740 mm2), respectively. The 64-element phased array is built as a complete reticle and includes 64 independent transmit channels with 5-b phase control, 3-b (9 dB) amplitude control, a saturated output power of 3 dBm at the antenna port, a 1-64 distribution network with redundant line amplifiers, and a high-efficiency on-chip antenna at each element. In addition, redundant serial digital interface and power strips, dual series metal-insulator-metal capacitors, and multiple RF inputs are employed for improved yield. The 256-element array uses the same phased-array blocks as the 64-element design, but is built using a subreticle stitching technique so as to result in a chip which is larger than the standard reticle size (22 × 22 mm2). The 64and 256-element arrays result in a half-power beamwidth of 12° and 6° in the E- and H-planes, a directivity of 23 and 29 dB, respectively, and scan to ±55° in the E- and H-planes with near-ideal patterns and a crosspolarization level of lesser than -30 dB. The measured equivalent isotropically radiated power (EIRP) of the 64-element array is 38 dBm at 62 GHz with a 3-dB bandwidth of 61-63 GHz, while that of the 256-element array is 45 dBm at 61 GHz with a 3-dB beamwidth of 58-64 GHz. A 1-4-Gb/s communication system is also demonstrated using the 64-element phased array up to ±45° scan angles, and at 4-, 30-, and 100-m ranges. To the best of our knowledge, this paper represents the first demonstration of large size (64and 256-element) phased-array transmitters on a single wafer.

A 1.1-Gbit/s 10-GHz Outphasing Modulator With 23-dBm Output Power and 60-dB Dynamic Range in 45-nm CMOS SOI

A 10-GHz outphasing modulator is implemented in a 45-nm CMOS silicon-on-insulator process. The modulator is designed to provide high linearity and can operate at high data rates by using 256-QAM while maintaining low error vector magnitude (EVM). Four high-speed 10-bit digital-to-analog converters (DACs) are integrated with dual in-phase and quadrature upconverters. To deliver high output power to an off-chip power amplifier, stacked field-effect transistor current buffers are used to isolate the modulator from the load and mitigate device breakdown. As a result, this modulator delivers 23 dBm to a differential 100- Ω load. The high-resolution DACs provide a fine control of the phase between the outphased signals and support more than 60 dB of dynamic range and power steps smaller than 1 dB over the entire output power range. The outphasing modulator demonstrates an EVM of 2.2% at 80 Mbit/s and an EVM of 3.4% at 1.1 Gbit/s for 256-QAM. To our knowledge, this is the first demonstration of an outphasing modulator operating above 1 Gb/s.

A 60 GHz 64-element phased-array beam-pointing communication system for 5G 100 meter links up to 2 Gbps

This paper presents a 60 GHz communication link system and measurements using a 64-element phased array transmitter. The transmit array includes high-efficiency on-wafer antennas, 3-bits amplitude and 5-bits phase control on each element, a measured saturated EIRP of 38 dBm at 60 GHz and scans to +/- 55° in the E- and H-planes with near-ideal patterns and low sidelobes. The phased-array transmitter is used in a 60 GHz communication link with an external up-conversion mixers and a Keysight 802.11ad waveform generator. A standard gain horn with a gain of 20 dB is used as the receiver, coupled to a Keysight high-speed digital demodulation scope. The communication link achieves a 16-QAM modulation with 3.85 Gbps at 4 m (full 802.11ad channel) and a QPSK modulation with 1.54 GBps over 100 m while scanning to +/-45° in both planes.

A 2–15-GHz Accurate Built-in-Self-Test System for Wideband Phased Arrays Using Self-Correcting Eight-State

A built-in-self-test (BIST) system for wideband phase arrays channels is presented. The BIST is implemented using an on-chip in-phase/quadrature (I/ Q) receiver with an integrated ring oscillator that provides both the channel test signal and the mixer local oscillator (LO). The BIST achieves wideband accuracy for relative phase and gain measurements at 2-15 GHz with a one-time self-correction algorithm with eight LO phases. The sequential algorithm determines the I/ Q errors, such as dc offset, gain and phase imbalances from the I/ Q outputs resulting from different LO phase states. An rms power detector network is also implemented for absolute gain measurements. The BIST can operate at rates >1 MHz (less than 1-μs sampling time) with signal-to-noise ratio greater than 50 dB and provides measurements that agree well with the vector network analyzer S-parameter data over a wide frequency range. To the best of our knowledge, this is the first implementation of high accuracy wideband BIST system for phased-array channels.

I/Q

This work presents a 60 GHz two-stage low-noise amplifier (LNA) without the use of a base inductor. A common emitter (CE) stage followed by a cascode (CC) stage is chosen to achieve a low noise figure (NF) with high gain. The LNA is designed in the Jazz SBC18H3 process technology, exhibits 15 dB gain with a 3-dB bandwidth of 14 GHz (52–66 GHz), has a minimum NF of 3.3 dB and an input Pids of −13.5 dBm ±0.5 dB with 19.6 mW of power consumption. A detailed set of experiments are presented to eliminate the uncertainties and errors, such as ENR data and measurement components, in the noise figure measurement set-up at mm-wave frequencies.

Mixers

This paper presents a 64 GHz transmit/receive communication link between two 32-element SiGe-based phased arrays. The antenna element is a series-fed patch array, which provides directivity in the elevation plane. The transmit array results in an EIRP of 42 dBm, while the receive array provides an electronic gain of 33 dB and a system NF < 8 dB including the T/R switch and antenna losses. The arrays can be scanned to +/−50° in the azimuth using a 5-bit phase shifter on the SiGe chip, while keeping very low sidelobes and a near-ideal pattern. The communication link uses one array on the transmit side and another array on the receive side, together with external mixers and IF amplifiers. A Keysight M8195A arbitrary waveform generator is used to generate the modulated waveforms on the transmit side and a Keysight DSO804A oscilloscope is used to demodulate the received IF signal. The link performance was measured for different scan angles and modulation formats. Data rates of 1 Gbps using 16-QAM and 2 Gbps using QPSK are demonstrated at 300 m. The system also results in > 4 Gbps data rate at 100 meters, and ∼ 500 Mbps data rate at 800 meters.

A wideband 60 GHz LNA with 3.3 dB minimum noise figure

Presents a summary of the millimeter-wave wafer-scale phased array work at UCSD. This concept can drastically reduce the cost of millimeter-wave phased arrays by combining the RFIC blocks, antennas, power distribution and summing, digital control and up and down converters all on the same wafer (or large piece of silicon), and eliminates all RF transitions in and out of the chip, therefore resulting in more efficient systems and lower cost systems. Examples at 90-100 GHz, 108-114 GHz and 400 GHz will be presented in this paper, together with their measured antenna patterns.