Tumay Kanar

Experimental Validation of Performance Limits and Design Guidelines for Small Antennas

The theoretical limit for small antenna performance that was derived decades ago by Wheeler and Chu governs design tradeoffs for size, bandwidth, and efficiency. Theoretical guidelines have also been derived for other details of small antenna design such as permittivity, aspect ratio, and even the nature of the internal structure of the antenna. In this paper, we extract and analyze experimental performance data from a large body of published designs to establish several facts that have not previously been demonstrated: (1) The theoretical performance limit for size, bandwidth, and efficiency are validated by all available experimental evidence. (2) Although derived for electrically small antennas, the same theoretical limit is also generally a good design rule for antennas that are not electrically small. (3) The theoretical predictions for the performance due to design factors such as permittivity, aspect ratio, and the internal structure of the antenna are also supported by the experimental evidence. The designs that have the highest performance are those that involve the lowest permittivity, have an aspect ratio close to unity, and for which the fields fill the minimum size enclosing sphere with the greatest uniformity. This work thus validates the established theoretical design guidelines.

A 90–100-GHz 4

This paper presents a 4 × 4 transmit/receive (T/R) SiGe BiCMOS phased-array chip at 90-100 GHz with vertical and horizontal polarization capabilities, 3-bit gain control (9 dB), and 4-bit phase control. The 4 × 4 phased array fits into a 1.6×1.5 mm2 grid, which is required at 94 GHz for wide scan-angle designs. The chip has simultaneous receive (Rx) beam capabilities (V and H) and this is accomplished using dual-nested 16:1 Wilkinson combiners/divider with high isolation. The phase shifter is based on a vector modulator with optimized design between circuit level and electromagnetic simulation and results in 1 dB and gain and phase error, respectively, at 85-110 GHz. The behavior of the vector modulator phase distortion versus input power level is investigated and measured, and design guidelines are given for proper operation in a transmit (Tx) chain. The V and H Rx paths result in a gain of 22 and 25 dB, respectively, a noise figure of 9-9.5 (max. gain), and 11 dB (min. gain) measured without the T/R switch, and an input P1 dB of -31 to -26 dBm over the gain control range. The measured output Psat is ~ -5 dBm per channel, limited by the T/R switch loss. Measurements show ±0.6- and ±0.75-dB variation between the 4 × 4 array elements in the Tx mode (Psat) and Rx mode, respectively, and 40-dB coupling between the different channels on the chip. The chip consumes 1100 mA from a 2-V supply in both the Tx and Rx modes. The design can be scaled to >10 000 elements using polyimide redistribution layers on top of the chip and the application areas are in W-band radars for landing systems.

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This paper presents the first built-in self-test system (BIST) for W-band transmit-receive phased-array modules. Low-loss high-isolation switches are attached to the RF input and output ports using λ/4 transmission-line sections, which result in a high shunt impedance when the BIST is disabled and minimal penalty in additional loss. A W-band in-phase/quadrature down-conversion mixer/receiver with 0.5-dB amplitude and 4°-5° phase imbalance at 90-100 GHz is also implemented on-chip and is used as an on-chip vector network analyzer. The BIST allows the measurement of the normalized S21 in both transmit and receive modes with high accuracy (4-bit phase response, 0.5-dB amplitude variation) at 90-100 GHz without any external calibration. The BIST also results in a normalized frequency response that agrees well with the measured S-parameters at 90-100 GHz.

4 SiGe BiCMOS Polarimetric Transmit/Receive Phased Array With Simultaneous Receive-Beams Capabilities

This talk will present our latest work on silicon RFICs for phased-array applications with emphasis on very large chips with built-in-self-test capabilities for 5G systems. SiGe is shown to be ideal for mm-wave applications due to its high temperature performance (automotive radars, base-stations, defense systems, etc.) and lower power consumption. These chips drastically reduce the cost of microwave and millimeter-wave phased arrays by combining many elements on the same chip, together with digital control and some cases, high-efficiency antennas. The phased-array chips also result in an easier packaging scheme using either a multi-layer PCB or wafer-level packages. We believe that this family of chips will be essential for millimeter-wave 5G communication systems.

A 90–100-GHz Phased-Array Transmit/Receive Silicon RFIC Module With Built-In Self-Test

This paper presents a low-noise SiGe radiometer at 136 GHz developed in an IBM 90-nm SiGe BiCMOS technology. The radiometer consists of a three-stage cascode low-noise amplifier with a gain of 36 dB, and a differential output square-law detector, all on a single chip. The detector results in responsivity of 11 kV/W and a noise equivalent power (NEP) of 0.6 pW/Hz1/2 at D-band frequencies. The radiometer chip consumes 45 mW and results in a minimum NEP of 1.4 fW/Hz1/2 with a peak responsivity of 52 MV/W at 136 GHz. The single-chip radiometer is suitable for high-resolution imaging systems having a noise bandwidth > 10 GHz and a low 1/f corner frequency . For an integration time of 3.125 mS (τ = 3.125 mS), the temperature resolution [noise equivalent temperature difference (NETD)] is determined to be 0.25 K using several different independent methods, and is the lowest NETD demonstrated in silicon technologies at D-band frequencies. This state-of-the-art performance is comparable to the best III-V imaging systems and proves that the advanced SiGe technology is a reliable option for imaging and radiometry applications.

Millimeter-wave large-scale phased-arrays for 5G systems

A 2-15 GHz SiGe VCO (voltage controlled oscillator) has been developed with a very low harmonic content. The design is based on the harmonic cancellation concept and uses a multiple-phase ring oscillator together with a wide-band active-weighted summer. The VCO results in an output power of -8 to -6 dBm and <; -50 dBc 3rd and 5th harmonic level at 2-15 GHz. The active area of the chip is very small (0.67 × 0.25 mm2) due to the lack of inductors, and the power consumption is 88-120 mW from a 2.5 V supply. To our knowledge, this is the first demonstration of a wide-band VCO showing a near-perfect sinewave output over a wide frequency range. The application areas are in built-in-self-test sources for wide-band radios and phased arrays.

A Low-Power 136-GHz SiGe Total Power Radiometer With NETD of 0.25 K

This paper presents a 4×4 transmit/receive SiGe BiCMOS phased array at 90-100 GHz with vertical and horizontal polarization capabilities, and 3-bit amplitude and 4-bit phase control. The 4×4 phased array fits into a 1.6×1.5 mm2 grid, which is required at 94 GHz for wide scan-angle designs. This is accomplished using dual-nested 16:1 Wilkinson combiners/divider with > 40 dB isolation between the dual-receive beams. Measurements show ±0.6 dB and ±0.75 dB variation between the array elements in the transmit (Psat) and receive mode, and <; -40 dB coupling between the elements for transmit, receive and dual-receive modes. The application areas are in W-band radar systems.

A 2-15 GHz VCO With Harmonic Cancellation for Wide-Band Systems

A built-in-self-test (BIST) system for wide-band phase arrays channels is presented. The BIST is implemented using an on-chip I/Q receiver with an integrated ring-oscillator that provides both the channel test signal and the mixer local oscillator (LO). The BIST achieves wide-band accuracy for relative phase and gain measurements at 2-15 GHz using a one-time self-correction algorithm with 8 LO phases. The BIST measurements agree well with the VNA S-parameter data over a wide frequency range. To our knowledge, this is the first implementation of high accuracy wide-band BIST system for phased-array channels.

A 90–100 Ghz 4×4 sige BiCMOS polarimetric transmit-receive phased array with simultaneous receive-beams capabilities

A built-in-self-test (BIST) system for wideband phase arrays channels is presented. The BIST is implemented using an on-chip in-phase/quadrature (I/ Q) receiver with an integrated ring oscillator that provides both the channel test signal and the mixer local oscillator (LO). The BIST achieves wideband accuracy for relative phase and gain measurements at 2-15 GHz with a one-time self-correction algorithm with eight LO phases. The sequential algorithm determines the I/ Q errors, such as dc offset, gain and phase imbalances from the I/ Q outputs resulting from different LO phase states. An rms power detector network is also implemented for absolute gain measurements. The BIST can operate at rates >1 MHz (less than 1-μs sampling time) with signal-to-noise ratio greater than 50 dB and provides measurements that agree well with the vector network analyzer S-parameter data over a wide frequency range. To the best of our knowledge, this is the first implementation of high accuracy wideband BIST system for phased-array channels.

A 2-15 GHz built-in-self-test system for wide-band phased arrays using self-correcting 8-state I/Q mixers

This paper presents a low-noise SiGe radiometer at 136 GHz developed in an IBM 90 nm SiGe BiCMOS technology. The radiometer chip consumes 45 mW and results in a minimum NEP of 1.4 fW/Hz½ with a peak responsivity of 52 MV/W at 136 GHz and a noise equivalent temperature difference (NETD) of 0.25K (τ = 3.125 mS). To the best of our knowledge, this is the lowest temperature resolution in silicon technologies at D-band.