Sami Kirolos

Theory and Implementation of an Analog-to-Information Converter using Random Demodulation

The new theory of compressive sensing enables direct analog-to-information conversion of compressible signals at sub-Nyquist acquisition rates. The authors develop new theory, algorithms, performance bounds, and a prototype implementation for an analog-to-information converter based on random demodulation. The architecture is particularly apropos for wideband signals that are sparse in the time-frequency plane. End-to-end simulations of a complete transistor-level implementation prove the concept under the effect of circuit nonidealities.

Random Sampling for Analog-to-Information Conversion of Wideband Signals

We develop a framework for analog-to-information conversion that enables sub-Nyquist acquisition and processing of wideband signals that are sparse in a local Fourier representation. The first component of the framework is a random sampling system that can be implemented in practical hardware. The second is an efficient information recovery algorithm to compute the spectrogram of the signal, which we dub the sparsogram. A simulated acquisition of a frequency hopping signal operates at 33times sub-Nyquist average sampling rate with little degradation in signal quality

A prototype hardware for random demodulation based compressive analog-to-digital conversion

In this paper, we utilize recent advances in compressive sensing theory to enable signal acquisition beyond Nyquist sampling constraints. We successfully recover signals sampled at sub-Nyquist sampling rates by exploiting additional structure other than bandlimitedness. We present a working prototype of compressive analog-to-digital converter (CADC) based on a random demodulation architecture. The architecture is particularly suitable for wideband signals that are sparse in the time-frequency plane. CADC has the advantage of enhancing the performance of communication and multimedia systems by increasing the transmission rate for the same bandwidth. We report successful reconstruction of AM modulated signals at sampling rates down to 1/8 of the Nyquist-rate, which represents an up to 87.5% savings in the bandwidth and the storage memory.

Thermally robust clocking schemes for 3D integrated circuits

3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers. However, dissipating the heat generated in the 3D chips possesses a major challenge to the success of the technology and is the subject of active current research. Since the generated heat degrades the performance of the chip, thermally insensitive/adaptive circuit design techniques are required for better overall system performance. In this paper, we propose a thermally adaptive 3D clocking scheme that dynamically adjusts the driving strengths of the clock buffers to reduce the clock skew between terminals. We investigate the relative merits and demerits of two alternative clock tree topologies in this work. Simulation results demonstrate that our adaptive technique is capable of reducing the skew by 61.65% on the average, leading to much improved clock synchronization and design performance in the 3D realm.

Adaptive SRAM design for dynamic voltage scaling VLSI systems

In this paper, we present an adaptive eight-transistor SRAM design that is capable of extending the operation of SRAM cells in the subthreshold region as well as maintaining high performance at the nominal supply voltages. The effective PMOS transistor size is dynamically adjusted according to the value of the supply voltage in order to sustain a balanced voltage transfer characteristics over the range of supply voltage operation. Simulation results demonstrate a power saving of up to 25% using our adaptive SRAM cell designed to maintain acceptable static noise margins under supply voltage in the range of 0.2 V to 1.2 V. The adaptive SRAM is very efficient for VLSI systems working under dynamic voltage scaling schemes, where the system is required to function at a variable supply voltage that extends to the subthreshold region of operation.

Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers

On-chip temperature gradient emerged as a major design concern for high performance integrated circuits for the current and future technology nodes. Clock skew is an undesirable phenomenon for synchronous digital circuits that is exacerbated by the temperature difference between various parts of the clock tree. We investigate the effect of on-chip temperature gradient on the clock skew for a number of temperature profiles. As an effective way of mitigating the clock skew, we present an adaptive circuit technique that senses the temperature of different parts of the clock tree and adjusts the driving strengths of the corresponding clock buffers dynamically to reduce the clock skew. Simulation results demonstrate that with minimal area overhead our adaptive technique is capable of reducing the skew by 72.4%, on the average, leading to much improved clock synchronization and design performance

Power-supply-variation-aware timing analysis of synchronous systems

With state of the art technology scaling, the problem of delay variability due to power supply variations is becoming more and more critical. This paper addresses the problem of analyzing the speed degradation in synchronous systems caused by power supply IR-drop in deep submicron CMOS devices. Considering the impact of power supply variation on the clock skew value, violations of the timing constraints equations are presented. To satisfy the timing constraints over a range of 20% of VDD variation, a 42% increase in the operational clock period has to be met with circuits operating at 2 GHz and implemented on 65 nm CMOS technology.

Accurate analytical delay modeling of CMOS clock buffers considering power supply variations

In this paper, we present an accurate method for analytical derivation of CMOS clock buffers delay under power supply variations. The method involves modeling of the pull-up and pull-down resistances using approximated drain saturation current device equations for the buffers together with lumped resistive capacitive elements for the interconnects. Compared to circuit simulation results, the analytical model provides more than four orders of magnitude speedup while maintaining an average error of 0.26% with 3.0% standard deviation over the entire range of power supply and circuit parameters variations, making it suitable for timing analysis and optimization.

Mitigating power-supply induced delay variations using self adjusting clock buffers

Aggressive technology scaling tends to reduce integrated circuits resilience against environmental variations. In this paper, we present an adaptive clock buffer circuit design and an adaptive clock distribution network (CDN) to improve chip performance and reliability in the presence of on-chip power-supply variations. The adaptive buffer provides a supply insensitive propagation delay to minimize the supply variation induced clock skew in clock distribution networks. Experimental results show that our technique reduces supply variation induced clock skew by at least 85% in a typical seven level clock tree architecture as compared to a nonadaptive worst case CDN, which represents up to 40% reduction in cycle time in state of the art processors.

Estimation of Capacitive Crosstalk-Induced Short-Circuit Energy

In the nanometer regime, crosstalk significantly impacts the dynamic power consumption of a chip. In this paper, we present a methodology for analyzing crosstalk-induced short-circuit power dissipation in cell-based digital designs. We introduce a new cell pre-characterization technique for facilitating the estimation of crosstalk-induced short-circuit power. Examples demonstrate that the presented methodology is three orders of magnitude faster than circuit simulators while the average error is as low as 3.5%.