Mosin Mondal

Thermally robust clocking schemes for 3D integrated circuits

3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers. However, dissipating the heat generated in the 3D chips possesses a major challenge to the success of the technology and is the subject of active current research. Since the generated heat degrades the performance of the chip, thermally insensitive/adaptive circuit design techniques are required for better overall system performance. In this paper, we propose a thermally adaptive 3D clocking scheme that dynamically adjusts the driving strengths of the clock buffers to reduce the clock skew between terminals. We investigate the relative merits and demerits of two alternative clock tree topologies in this work. Simulation results demonstrate that our adaptive technique is capable of reducing the skew by 61.65% on the average, leading to much improved clock synchronization and design performance in the 3D realm.

Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations

A network-on-chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected through programmable crosspoints. Since an NoC may provide a number of paths between a given source and destination, manufacturing or runtime faults on one interconnect does not necessarily render the chip useless. It is partly because of this fault tolerance that NoCs have emerged as a viable alternative for implementing communication between functional units of a chip in the nanometer regime, where high defect rates are prevalent. In this paper, the authors quantify the fault tolerance offered by an NoC against process variations. Specifically, the authors develop an analytical model for the probability of failure in buffered global NoC links due to interconnect dishing, and effective channel length variation. Using the developed probability model, the authors study the impact of link failure on the number of cycles required to establish communications in NoC applications

Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance

The increasing demand for high performance ICs and system on chip necessitates reliable methodologies for reducing pessimism in chip design. In this paper, we investigate how the frequency dependence of loop self inductance affects the RLC delay. We show that the pessimism in the estimation of RLC propagation delay could be as high as 30% if the frequency dependence of inductance is not considered properly. As a means of efficiently computing less pessimistic RLC delay values, we present an analytical model of frequency dependent loop self inductance that can be applied to model a wide range of real design scenarios. We demonstrate that our approach is computationally efficient and produces accurate and realistic (less pessimistic) delay values that lead to significantly improved system performance.

Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect

Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnect. In this paper, we evaluate the performance and reliability of nanotube bundles for future VLSI applications. We develop a scalable equivalent circuit model that captures the statistical distribution of metallic nanotubes while accurately incorporating recent experimental and theoretical results on inductance, contact resistance, and ohmic resistance. Leveraging the circuit model, we examine the performance and reliability of nanotube bundles including inductive effects. The results indicate that SWCNT interconnect bundles can provide significant improvement in delay over copper interconnect depending on the bundle geometry and process technology.

Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers

On-chip temperature gradient emerged as a major design concern for high performance integrated circuits for the current and future technology nodes. Clock skew is an undesirable phenomenon for synchronous digital circuits that is exacerbated by the temperature difference between various parts of the clock tree. We investigate the effect of on-chip temperature gradient on the clock skew for a number of temperature profiles. As an effective way of mitigating the clock skew, we present an adaptive circuit technique that senses the temperature of different parts of the clock tree and adjusts the driving strengths of the corresponding clock buffers dynamically to reduce the clock skew. Simulation results demonstrate that with minimal area overhead our adaptive technique is capable of reducing the skew by 72.4%, on the average, leading to much improved clock synchronization and design performance

Parameter-Variation-Aware Analysis for Noise Robustness

This paper studies the impact of variability on the noise robustness of logic gates using noise rejection curves (NRCs). NRCs allow noise pulses to be modeled using magnitude-duration profiles, and can be used to derive a noise susceptibility metric for the noise robustness of logic gates. Analytical methods - based upon calibration runs in circuit simulators - to determine noise susceptibility in the presence of variations in process, design, and environmental parameters (Leff, VT, VDD, and W) are described. Such analytical methods can be used not only to accurately estimate the impact of variability on noise robustness, but also to optimize designs for noise robustness

Estimation of Capacitive Crosstalk-Induced Short-Circuit Energy

In the nanometer regime, crosstalk significantly impacts the dynamic power consumption of a chip. In this paper, we present a methodology for analyzing crosstalk-induced short-circuit power dissipation in cell-based digital designs. We introduce a new cell pre-characterization technique for facilitating the estimation of crosstalk-induced short-circuit power. Examples demonstrate that the presented methodology is three orders of magnitude faster than circuit simulators while the average error is as low as 3.5%.

Analytical modeling of loop self inductance bound for inductance-aware physical synthesis

An analytical model of loop self inductance bound has been developed that is applicable to a wide range of layout geometries commonly encountered in high performance integrated circuits. When compared with field solver results, the developed model shows an average error of 2.03%. A speedup of more than three orders of magnitude is obtained, enabling our model to be suitable for application in inductance aware physical synthesis. The accurate upper bound of inductance provided by our model can also be used for inductance screening and pre-layout inductance estimation

A model-based technique for efficient evaluation of noise robustness

In this paper, we present an analytical technique for deriving noise rejection curves (NRCs) and the associated noise susceptibility metric under parameter variations (Leff, VT, VDD and channel width, W). The method involves modeling of the pull-up and pull-down resistances using approximated BSIM4 device equations. Compared to circuit simulation results, the analytical model provides more than live orders of magnitude speedup while maintaining an average (maximum) error of 1.3% (5%) over the entire range of parameter variations, which makes it suitable for design optimization for noise robustness.

Accurate Loop Self Inductance Bound for Efficient Inductance Screening

An analytical model for the upper bound of loop self inductance has been developed that is applicable to a wide range of layout geometries commonly encountered in high performance integrated circuits. We demonstrate that the existing analytical models can significantly underestimate the value of loop self inductance producing optimistic results. When compared with field solver results, the developed model shows an average error of 2%. A speedup of more than three orders of magnitude is obtained enabling our model to be fit for applications in inductance screening, inductance aware physical synthesis and prelayout inductance estimation