Samir Roy

KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer

In the domain of combinational logic synthesis, logic minimization plays a vital role in determining the area and performance of the synthesized circuit. Logic minimization based on AND-OR decomposition of functions is a well studied area. However, minimization based on AND-XOR decomposition has received relatively lesser attention. Since many real-life combinational functions are XOR dominated, a logic minimizer producing efficient AND-XOR decomposition can lead to more efficient realization of such circuits. The computer-aided design tool KGPXORMIN presented in this paper is a multilevel AND-XOR minimizer which outperforms the scheme reported by Saul (1991) by 45.77% in the literal count metric. In general, most of the real-life and benchmark circuits are a combination of OR and XOR logic. In order to have area efficient realization, we need to have an efficient minimizer capable of judicious use of OR and XOR gates. An integrated tool KGPMIN has been developed which combines the AND-XOR minimizer KGPXORMIN and well-known AND-OR minimizer MISII. Depending on the measure of dominance of OR and XOR logic, it switches from one minimizer to the other during the decomposition phase. By judicious switching from one minimizer to the other, on the average, KGPMIN outperforms MISII by 64.08% in literal count and 45.16% in absolute gate area for the MCNC combinational logic benchmarks. It also outperforms KGPXORMIN by 17.46% in literal count and 34.32% in gate area. The number of levels of the circuits synthesized with KGPMIN can be found to be comparable with the figures arrived at from the application of MISII.

Synthesis of highly testable fixed-polarity AND-XOR canonical networks-A genetic algorithm-based approach

Specific inherent advantages of AND-XOR networks have encouraged researchers to look for efficient minimization and synthesis tools for their realization. Among several canonical representations of AND-XOR networks, the most easily testable one is the fixed polarity Consistent Generalized Reed Muller (CGRM) form. In this paper, a Genetic Algorithm (GA) formulation of the problem of finding the polarity of the variables resulting in minimum number of product terms has been proposed. The quality of the solution obtained and the high rate of convergence have established the effectiveness of the genetic algorithm in solving this particular NP-hard problem. Further, the inherent parallelism of genetic algorithm makes the proposed scheme an ideal candidate for solving the problem in a multiprocessor environment.

Minority gate oriented logic design with quantum-dot cellular automata

This paper presents novel combinational logic designs with plus-shaped quantum-dot cellular automata (QCA) using minority gate as the fundamental building block Present CMOS technology of VLSI design is fast approaching its fundamental limit, and researchers are looking for a nano-scale technology for future ICs in order to continue the pace of circuit miniaturization predicted by Moores law even beyond 2016 QCA is considered to be a promising technology in this regard This paper provides the fundamentals of QCA followed by the proposed QCA structure realizing a minority gate, given by the Boolean expression m (x1, x2, x3) = x1′.x2′+x2′.x3′+x3′.x1′ Universality of minority gate is established, and minority gate oriented design principles are provided Minority gate oriented designs for XOR and full adder are presented Simulation results show the effectiveness of the proposed designs.

Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area

This paper reports the design of BIST structures for sequential machines. Testability of an FSM is limited due to the fact that some machine states remain unreachable and some act as a sink under any input sequence. The proposed scheme provides uniform mobility, referred to as degree of freedom, among the machine states in test mode by enhancing the reachability and emitability of the states. Uniform mobility of states ensures higher fault efficiency in a BIST structure. A graph based approach is introduced for state code assignment to minimize gate area. Experimental results on benchmark circuits establish that the proposed scheme does improve the BIST quality simultaneously reducing the gate area of the synthesized machine.

A Novel Semantic Similarity Based Technique for Computer Assisted Automatic Evaluation of Textual Answers

We propose in this paper a unique approach for the automatic evaluation of free text answers. A question answering module has been developed for the evaluation of free text responses provided by the learner. The module is capable of automatically evaluating the free text response of the learner SA to a given question Q and its model text based answer MA on a scale [0, 1] with respect to the MA. This approach takes into consideration not only the important key-words but also stop words and the positional expressions present in the learners’ response. Here positional expression implies the pre-expression and post-expression appearing before and after a keyword in the learners’ response. The results obtained on using this approach are promising enough for investing into future efforts.

Cellular Automata Based Encompression Technology for Voice Data

This paper reports an efficient compression technology for voice data. It is developed around Programmable Cellular Automata (PCA) structure. The program executed on PCA is so designed that it ensures high speed transmission of voice data with desired level of security (encryption). Further, the regular and local neighborhood structure of CA is employed to design high speed low cost implementation of the encompression (encryption + compression) scheme. Comparison with standard GSM (Global System Mobile) technology, in respect of compression ratio, the quality of D’encompressed voice data and the quality of security attained, confirms high potential of the proposed scheme.

Enhancing BIST quality of sequential machines through degree-of-freedom analysis

Designing a BIST structure for sequential circuits is rather a complex problem as some states remain unreachable and some act as the sink under any input sequence. This paper reports an efficient scheme to provide uniform mobility, referred to as degree of freedom, in a sequential machine by enhancing the reachability as well as the emittability of the states. The uniform mobility of states ensures higher fault efficiency in a BIST structure of the circuit. Moreover, as a non-scan scheme, the technique provides lower test application time and at-speed testing.

Cellular automata based test structures with logic folding

This work presents an efficient test solution for VLSI circuits. The test structure is designed with GF(2/sup P/) CA. The introduction to an innovative scheme of logic folding optimizes the cost of test logic that can not be feasible with the flattened structure of GF(2) CA/LFSR.

Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture

Due to the low design turn-around time, low risk, high testability, and field programmability, Field Programmable Gate Arrays are becoming increasingly popular for rapid circuit realization. The logic blocks in currently available FPGAs are mostly single output. This accompanied with their inability to realize XORs efficiently and the absence of good logic synthesis tools for XOR functions, prevents their usage in many real-life XOR dominated applications. In this paper, we propose a new 5-input 3-output AND-XOR based logic block architecture built around Cellular Automata Array (CAA). An efficient multi-level AND-XOR minimizer has been developed. A generic library based technology mapping technique has been evolved. Experimentation with a large number of XOR dominated MCNC benchmarks establishes the superiority of our logic block over those of Xilinx and Actel for these functions. The mapping scheme is a generic one and thus can be used to evaluate any arbitrary multi-output as well as single-output logic block.

Intelligent fuzzy spelling evaluator for e-Learning systems

Evaluating Learners’ Response in an e-Learning environment has been the topic of current research in areas of Human Computer Interaction, e-Learning, Education Technology and even Natural Language Processing. The current paper presents a twofold strategy to evaluate single word response of a learner in an e-Learning environment. The response of the learner to be evaluated would consist of errors committed due to lack of knowledge and also out of inadvertent mistakes committed while typing the answers. The proposed system benevolently considers such errors and still marks the learner partially. The feature incorporated in this work adds the human element to the mechanised system of evaluation and assessment in an e-Learning environment.