Debesh K. Das

On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set

Logic synthesis with reversible circuits has received considerable interest in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Newer technologies like ion trapping or nuclear magnetic resonance are required to emulate quantum gates. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely, single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate fault (MMGF), have been found to be more suitable for modeling defects in quantum k-CNOT gates. In this paper, it is shown that in an (n times n) reversible circuit implemented with k-CNOT gates, addition of only one extra control line along with duplication each k-CNOT gate yields an easily testable design, which admits a universal test set of size (n +1) that detects all SMGFs, RGFs, and PMGFs in the circuit.

Testable design of non-scan sequential circuits using extra logic

Design of irredundant and fully testable non-scan synchronous sequential circuits is a major concern of logic synthesis. The presence of sequentially redundant faults (SRFs) makes test generation complicated, and hence their removal is highly desirable to enhance testability. In this paper, we propose a novel technique for testable design which is significantly different from scan designs, or testability-targeted synthesis approaches. We show that addition of some extra logic and a control input to an arbitrary sequential circuit can eliminate all equivalent and isomorph SRFs, even under the multiple stuck-at-fault model. Every pair of states can easily be distinguished in the modified machine, thus making it easily testable. The augmented logic is also universal, i.e., independent of the state diagram or the circuit structure of the given machine. Analysis of benchmark circuits reveals that its hardware overhead is much less compared to that of full scan design.

Synthesis of symmetric functions for path-delay fault testability

A new technique of synthesizing totally symmetric Boolean functions is presented that achieves complete robust path-delay fault testability. We show that every consecutive symmetric function can be expressed as a logical composition (e.g., AND, NOR) of two unate symmetric functions, and the resulting composite circuit can be made robustly path-delay fault testable, if the constituent unate functions are synthesized as two-level irredundant circuits. Nonconsecutive symmetric functions can also be synthesized by decomposing them into a set of consecutive symmetric functions. The circuit cost of the proposed design can further be reduced by a novel algebraic factorization technique based on some combinatorial clues. The overall synthesis guarantees complete robust path-delay fault testability, and can be completed in linear time. The results shows that the proposed method ensures a significant reduction in hardware, as well as in the number of paths, which in turn, reduces testing time, as compared to those of the best-known earlier methods.

Design of an optimal test pattern generator for built-in self testing of path delay faults

A novel design of a test pattern generator (TPG) for built-in self-testing (BIST) of path delay faults, is proposed. For an n-input CUT, the TPG generates a sequence of length (n.2/sup n/+1), that includes all n.2/sup n/ single-input-change (SIC) test pairs, and hence optimal. The generation of such a sequence of minimum length (i.e., n.2/sup n/+1) was an open problem. A simple iterative circuit of the TPG is then constructed. This provides minimum test application time for testing path delay faults, and compares favorably with the earlier BIST designs.

Optimum Test Set for Bridging Fault Detection in Reversible Circuits

Testing of bridging faults in a reversible circuit is investigated in this paper. The intra-level single bridging fault model is considered here, i.e. any single pair of lines, both lying at the same level of the circuit, may be assumed to have been logically shorted in order to model a defect. For an (n X n) reversible circuit with d levels realized with simple Toffoli gates, the time complexity of the test generation procedure is O(nd2 log2n). A test set of cardinality O(d log2n) is found to be sufficient for testing all such detectable faults. A minimal test set can also be easily derived by using the concept of test equivalence.

Easily testable realization of GRM and ESOP networks for detecting stuck-at and bridging faults

A testable realization of Generalized Reed-Muller (GRM) or EXOR Sum-of-Products (ESOP) expression has been proposed that admits a combined universal test set of size (2n+6) for detection of stuck-at and bridging faults. For GRM implementation, the test set detects all single stuck-at and bridging faults (both OR and AND type) and a large number of multiple bridging faults. For ESOP, a few single bridging faults may remain untested, occurrence of which can be avoided by employing a design and layout technique. The test set is independent of the function and the circuit-under-test and can be stored in a ROM on chip for built-in self-test. For several benchmark circuits, the size of the test set is found to be much smaller than an ATPG-generated test set or those of the previous methods.

Fault diagnosis in reversible circuits under missing-gate fault model

This article presents a novel technique for fault detection as well as fault location in a reversible combinational circuit under the missing gate fault model. It is shown that in an (nxn) reversible circuit implemented with k-CNOT gates, addition of only one extra control line along with duplication each k-CNOT gate, yields an easily testable design, which admits a universal test set (UTS) of size (n+1) that detects all single missing-gate faults (SMGFs), repeated-gate faults (RGFs), and partial missing-gate faults (PMGFs) in the circuit. Furthermore, storage of only one vector (seed) of the UTS is required; the rest can be generated by n successive cyclic bit-shifts from the seed. For fault location under the SMGF model, a technique for identifying the faulty gate is also presented that needs application of a single test vector, provided the circuit is augmented with some additional observable outputs.

Test generation for acyclic sequential circuits with hold registers

We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e., the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM. The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can also be performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.

Optimal Reversible Logic Circuit Synthesis Based on a Hybrid DFS-BFS Technique

Logic synthesis with reversible circuits has received considerable interest in the light of advances recently made in quantum computation. In this paper, we propose an improved technique for synthesizing reversible circuits based on a combined depth-first search (DFS) and breadth-first search (BFS) algorithm. A method based on DFS alone may often take a long time to converge, whereas, a BFS based method requires a large amount of memory for designing a circuit of moderate complexity. To strike a balance between these two approaches, we propose a hybrid DFS-BFS based synthesis algorithm that reduces the computation time compared to the DFS method and requires less space compared to the BFS method, while optimizing the cost of the circuit. Synthesis results on several reversible benchmark circuits have been reported.

Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults

A new testable realization of generalized Reed-Muller (GRM) expression with tree implementation of the EXOR-part is presented. This solves an open problem of designing an EXOR-tree based GRM network that admits a universal test set. For an n-variable function, the proposed design can be tested by (2n+8) test vectors, which are independent of the function and the circuit-under-test (CUT). Excepting a few intergate bridging faults in the EXOR-tree, it detects all other single bridging (both OR-and AND-type) and all single stuck-at faults. The EXOR-part is designed as a tree of depth (/spl lceil/log/sub 2/s/spl rceil/ +1), where s is the number of product terms in the given GRM expression. This reduces circuit delay significantly compared to cascaded EXOR-part. Further, for several benchmark circuits, the test set is found to be much smaller than those of the earlier tree-based designs.