Sampo Tuuna

High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling

High-performance long-range NoC link enables efficient implementation of network-on-chip topologies which inherently require high-performance long-distance point-to-point communication such as torus and fat-tree structures. In addition, the performance of other topologies, such as mesh, can be improved by using high-performance link between few selected remote nodes. We presented novel implementation of high-performance long-range NoC link based on multilevel current-mode signaling and delay-insensitive two-phase 1-of-4 encoding. Current-mode signaling reduces the communication latency of long wires significantly compared to voltage-mode signaling, making it possible to achieve high throughput without pipelining and/or using repeaters. The performance of the proposed multilevel current-mode interconnect is analyzed and compared with two reference voltage mode interconnects. These two reference interconnects are designed using two-phase 1-of-4 encoded voltage-mode signaling, one with pipeline stages and the other using optimal repeater insertion. The proposed multilevel current-mode interconnect achieves higher throughput and lower latency than the two reference interconnects. Its throughput at 8 mm wire length is 1.222 GWord/s which is 1.58 and 1.89 times higher than the pipelined and optimal repeater insertion interconnects, respectively. Furthermore, its power consumption is less than the optimal repeater insertion voltage-mode interconnect, at 10 mm wire length its power consumption is 0.75 mW while the reference repeater insertion interconnect is 1.066 mW. The effect of crosstalk is analyzed using four-bit parallel data transfer with the best-case and worst-case switching patterns and a transmission line model which has both capacitive coupling and inductive coupling.

Modeling of Energy Dissipation in RLC Current-Mode Signaling

In this paper, energy dissipation in resistance-inductance-capacitance (RLC) current-mode signaling is modeled. The energy dissipation is derived separately for driver, wire, and receiver termination. The effects of rise time and clock cycle are included. A realizable Π-model for the driving-point impedance of an RLC current-mode transmission line is derived. The output current of an RLC current-mode transmission line is also derived. The model is extended to multiple parallel coupled interconnects with inductive and capacitive coupling between them. The model is verified by comparing it to HSPICE in 65-nm technology and applied to differential current-mode signaling.

Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid

In this paper, an analytical model for the current draw of an on-chip bus is presented. The model is combined with an on-chip power supply grid model in order to analyze noise caused by switching buses in a power supply grid. The bus is modeled as distributed resistance-inductance-capacitance (RLC) lines that are capacitively and inductively coupled to each other. Different switching patterns and driver skewing times are also included in the model. The power supply grid is modeled as a network of RLC segments. The model is verified by comparing it to HSPICE. The error was below 8%. The model is applied to determine the influence of driver skewing times on maximum power supply noise.

Self-Timed Approach for Noise Reduction in NoC Reduction in NoC

A self-timed approach for minimizing crosstalk and switc hing noise is presented. It is based on self-timed circuit design techniques, system partitioning and time-interleaved communication. In this approach, time-interleaving is use d to reduce the effect of interconnect signal coupling, current peaks and the probabili ty of erroneous states. Timeinterleaving is implemented by dividing the system into partitions, which are desynchronized internally and with respect to the other within e same partition. The technique is based on re-tuning the timing using self-timed d sign. The impact of asynchronous signaling techniques on overall noise levels and ig al timing is studied in several contexts. The method was illustrated using two cas e studies. The first case study employed time-interleaving to reduce noise in high perform ance on-chip bus segments. The second one exploited the advantages of the de-synchronizatio method applied to the path metric unit of the Viterbi decoder. For the case studies w have used 0.13, 0.18 and 0.35 μm CMOS technologies.

Analytical model for crosstalk and intersymbol interference in point-to-point buses

In this paper, an analytical model to estimate crosstalk noise and intersymbol interference on capacitively and inductively coupled point-to-point on-chip buses is derived. The derived closed-form equation for output voltage enables the usage of the model in computer-aided design (CAD) tools for complex systems where high simulation speed is essential. The model also combines together properties such as inductive coupling, initial conditions, signal rise time, input phases, and bit sequences that have not been included in a single closed-form model before. The model is compared to HSPICE and previous models. The model and HSPICE are in good agreement with each other

Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation

In this paper, we model on-chip signaling over a bus consisting of encoding, drivers, transmission lines, receivers and decoding. We characterize the signaling circuitry as a function of its load capacitance. The effective load capacitance seen by a driver is derived for the decoupling method and distributed RLC transmission line models. The driver delay and rise time corresponding to the derived effective capacitance are used to derive the far-end voltage of a transmission line bus. The effects of process variation are taken into account in the characterization of the signaling circuitry and in the wire analysis. The overall delay variation of the bus due to device and wire process variation is then calculated. The model is verified by comparing it to HSPICE. We implement regular voltage mode, level- encoded dual-rail and l-of-4 signaling circuitry and apply the derived model to analyze them. The implementation and analysis are done in 45 nm technology.

Analysis of Crosstalk and Process Variations Effects on On-Chip Interconnects

We present analysis of crosstalk and process variations effects on reliability and signal propagation delay of two delay-insensitive on-chip interconnects. The first interconnect is designed using conventional two-phase dual-rail encoding using voltage-mode signaling. The second one uses current-mode signaling with new implementation of two-phase dual-rail encoding. It uses multi-current level and differential switching of dual-rail wires to indicate the data value and its validity respectively. Performance comparison between the two interconnects shows the novel differentially switching dual-rail link is faster compared to the conventional two-phase dual-rail one. The effect of crosstalk is analyzed using 4-bit parallel data transfer using transmission line model with capacitive and inductive coupling and 16 different switching patterns. We analyze the effect of process variations on reliability and delay in the presence of crosstalk by changing wire width by plusmn10% and thickness by -10%. In addition the effect of plusmn3sigma supply voltage variation on delay is studied. The circuit is designed and simulated using Cadence Analog Spectre and Hspice of 130nm CMOS technology

Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput

A high-throughput and low-energy semi-serial on-chip communication link based on novel design techniques and circuit solutions is presented. This self-timed link is designed using high-speed serialization/deserializtion and pulse dual-rail encoding techniques. The link also employs wave-pipelined differential pulse current-mode signaling to maintain the high speed data intake from the serializer. The energy efficiency of the proposed semi-serial link, which consists of bit-serial links in parallel, mainly comes from the sharing of the novel serializers control circuit among the bit-serial links. In addition, the integration of pulse signaling with wave-pipelining, the use of a new low-complexity data validity detection technique, and the avoidance of data decoding logic also contribute to the power reduction. Furthermore, the formulated pulse dual-rail encoding provides an opportunity to implement pulse signaling at no cost. The ability to detect data validity at bit level allows acknowledgment per word without losing the delay-insensitivity of the transmission. The proposed semi-serial link is analyzed and compared with bit-serial and fully bit-parallel links for 64-bit data and communication distances of 1 to 8 mm. The semi-serial link which consists of eight bit-serial links provides 72.72 Gbps throughput with 286 fJ/bit energy dissipation for 8 mm transmission. It dissipates the lowest energy per bit compared to fully bit-parallel links while achieving the same throughput. The links are designed and simulated in Cadence Analog Spectre using 65-nm technology from STMicroelectronics.

Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects

The authors present a performance boosting technique with a better power efficiency for delay-insensitive on-chip interconnects. The increase in signal propagation delay uncertainty with technology scaling makes self-timed delay-insensitive on-chip interconnects the most appropriate alternative. However, achieving high-performance communication in self-timed delay-insensitive links is difficult, especially for large bit parallel transmission because of the time-consuming detection of each bit validity. The authors present a high-speed completion detection technique along with its circuit implementation and two on-chip interconnects which use the proposed completion detection circuit. The performance, power consumption, power efficiency and area of the presented on-chip interconnects are analysed and compared with the conventionally implemented delay-insensitive interconnects. For 64-bit parallel transmission, 2.07 and 1.72 times throughput improvement with 47 and 39% more power efficiency have been achieved for the two interconnects compared to their conventional counterparts. The interconnect circuits are designed and simulated using Cadence Analog Spectre and Hspice with 65 nm complementary metal-oxide semiconductor technology from STMicroelectronics.

Estimation of crosstalk noise for on-chip buses

In this paper an analytical model to estimate crosstalk noise on capacitively and inductively coupled on-chip buses is derived. The analytical nature of the model enables its usage in complex systems where high simulation speed is essential. The model also combines together properties such as inductive coupling, initial conditions, signal rise time, switching time and bit patterns that haven’t been included in a single analytical crosstalk model before. The model is compared to three previous crosstalk noise estimation models. The error of the model remains below four percent when compared to HSPICE. It is also demonstrated that for planar buses the five closest neighboring wires constitute up to 95% of the total induced crosstalk noise.