San-Fu Wang

Energy efficiency of task allocation for embedded JPEG systems.

Embedded system works everywhere for repeatedly performing a few particular functionalities. Well-known products include consumer electronics, smart home applications, and telematics device, and so forth. Recently, developing methodology of embedded systems is applied to conduct the design of cloud embedded system resulting in the applications of embedded system being more diverse. However, the more energy consumes result from the more embedded system works. This study presents hyperrectangle technology (HT) to embedded system for obtaining energy saving. The HT adopts drift effect to construct embedded systems with more hardware circuits than software components or vice versa. It can fast construct embedded system with a set of hardware circuits and software components. Moreover, it has a great benefit to fast explore energy consumption for various embedded systems. The effects are presented by assessing a JPEG benchmarks. Experimental results demonstrate that the HT, respectively, achieves the energy saving by 29.84%, 2.07%, and 68.80% on average to GA, GHO, and Lin.

A MULTI-BAND LOW NOISE AMPLIFIER WITH GAIN FLATNESS AND BANDWIDTH ENHANCEMENT

In this paper, a differential multi-band CMOS low noise amplifier (LNA) is proposed that is operated within a range of 1500–2700 MHz with input matching capacitor switching and gain flatness performance enhancement technique. Traditional multi-band LNAs have poor performances on gain flatness performance. Therefore, we propose a new multi-band LNA which obtain good gain flatness performance by integrating the characteristics of the transistor trans-conductance and LC resonant load. The new LNA can also achieve a tunable frequency at different matching capacitance conditions. The post-layout simulation results shows that the voltage gain is between 19.3 dB and 22.4 dB, the NF is less than 2.5 dB, and the 1-dB compression point is about -5.1 dBm. The LNA consumes 17.79 mW under 1.8 V supply voltage in TSMC 0.18-um RF CMOS process.

Efficient energy exploration for embedded systems

Mobile and ubiquitous computation of embedded system exacerbates energy consumption. In this work, we propose minimum energy path (MEP) approach to improve energy efficiency for embedded system. The MEP adopts path-based strategy to constructs a set of path class. Each path comprises the number of tasks that will be sequentially determined the role depending on the energy consumption. As a result, the energy efficiency is gradually improved while sequential paths are progressively identified the role of tasks. Experimental results show that MEP that can achieve 7.88% energy saving on average in all cases.

Grey decision of optimal simultaneous mapping and clustering to improve FPGA performance

This work studies how the architectural parameters of LUT-based field programmable gate arrays (FPGAs) are related to the LUT cluster size N and input number k A novel algorithm is proposed to combine grey decision-making approach for solving the problem of FPGA performance. Experimental results demonstrate that the algorithm improves the DAO map+T-VPack delay by 7.27% and reduces the SMAC total of CLB number by 22.15% on average. Furthermore, our proposed can get optimizes performance by appropriate selection of pairs of LUT cluster size N and input number k to construct the FPGA architecture with inequality demandable weight in area, energy, and delay.

The scheduling and placement strategies for FPGA dynamic reconfigurable system

In recent years, the FPGA performance requirements are changes in the evolution. From the past a static schedule way, development tasks are running to the dynamic scheduling system. This study proposed FPGA dynamic reconfigurable scheduling and placement base on TGFF generated Random standard schedule and Grey relation of grey system. The scheduling method accords to the placement of strategy objectives mentioned in the different tasks and time, while the placement of the ideal state, the FPGA resources will improve utilization, and reduce waste. Finally, the results of the mentioned method strategy the placement make scheduling strategy referred to reach the ideal state.

Grey relational clustering associated with CAPRI applied to FPGA placement

Grey relational clustering is used to minimise wire length during field programmable gate arrays (FPGA) placement and routing. The proposed Grey Relational Clustering Apply to Placement (GRAP) algorithm combines grey relational clustering and convex assigned placement for regular ICs method to construct a placement netlist, which was successfully used to solve the problem of minimising wire length in an FPGA placement. Upon calculating the grey relational grade, GRAP can rank the sequence and analyse the minimal distance in configuration logic blocks based on the grey relational sequence and combined connection-based approaches. The experimental results demonstrate that the GRAP effectively compares the Hibert, Z and Snake with bounding box (BB) cost function in the space-filling curve. The GRAP improved BB cost by 0.753%, 0.324% and 0.096% for the Hilbert, Z and Snake, respectively. This study also compares the critical path with the space-filling curve. The GRAP approach improved the critical path for Snake by 1.3% in the space-filling curve; however, the GRAP increased critical path wire by 1.38% and 0.03% over that of the Hilbert and Z of space-filling curve, respectively.

Phase-locked loop design with fast-digital-calibration charge pump

A fast-digital-calibration technique is proposed for reducing current mismatch in the charge pump (CP) of a phase-locked loop (PLL). The current mismatch in the CP generates fluctuations, which is transferred to the input of voltage-controlled oscillator (VCO). Therefore, the current mismatch increases the reference spur in the PLL. Improving current match of CP will reduce the reference spur and decrease the static phase offset of PLLs. Moreover, the settling time, ripple and power consumption of the PLL are also improved by the proposed technique. This study evaluated a 2.27–2.88 GHz frequency synthesiser fabricated in TSMC 0.18 μm CMOS 1.8 V process. The tuning range of proposed VCO is about 26%. By using the fast-digital-calibration technique, current mismatch is reduced to lower than 0.97%, and the operation range of the proposed CP is between 0.2 and 1.6 V. The proposed PLL has a total power consumption of 22.57 mW and a settling time of 10 μs or less.

Grey relational grade applied to FPGA placement with minimal wire length

This work aims at developing grey relational grade for minimal wire length FPGA placement to follow-up the FPGA routing work. The proposed GRAP (Grey Relational Grade Apply to Placement) algorithm was combined with grey relational clustering and CAPRI algorithm to construct a placement netlist to successfully solve minimal wire length in FPGA placement design problem. After the grey relational grade is calculated, GRAP can rank the sequence and analyze the minimal distance in CLB blocks from the grey relational sequence and combine connection-based approaches. Experimental results demonstrate that the proposed algorithm can obtain minimal total wire length.