Yang-Hsin Fan

Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems

In this paper, we propose an enhancement partition method that incorporates formal partition, fitting system constraints and hardware orient partition algorithm to solve partitioning issue for embedded multiprocessor FPGA systems. With formal partition, we can rapidly obtain a set of partitioning results that satisfy the system constraints on the number of processors. To fit various system constraints, we find out all partition result sets by fitting system constraints. Finally, hardware orient partition can provide a nearly best partition result for designer to develop multiprocessors system-on-a-chip system. Experiment results show that the proposed method can obtain the fitting best partitioning result than other partitioning method using JPEG encoding system example.

Hardware-oriented Partition for Embedded Multiprocessor FPGA Systems

In this paper, we present hardware-oriented partitioning approach that can solve the partitioning issues for embedded multiprocessor FPGA systems. In addition, it can gain a better partitioning result, faster execution time, less memory and higher slice used rate, under satisfied system constraints. We also demonstrate the feasibility of our approach by a JPEG encoding system using Xilinx ML310 FPGA platform. Experiment results show that the execution time and memory size are improved.

Energy efficiency of task allocation for embedded JPEG systems.

Embedded system works everywhere for repeatedly performing a few particular functionalities. Well-known products include consumer electronics, smart home applications, and telematics device, and so forth. Recently, developing methodology of embedded systems is applied to conduct the design of cloud embedded system resulting in the applications of embedded system being more diverse. However, the more energy consumes result from the more embedded system works. This study presents hyperrectangle technology (HT) to embedded system for obtaining energy saving. The HT adopts drift effect to construct embedded systems with more hardware circuits than software components or vice versa. It can fast construct embedded system with a set of hardware circuits and software components. Moreover, it has a great benefit to fast explore energy consumption for various embedded systems. The effects are presented by assessing a JPEG benchmarks. Experimental results demonstrate that the HT, respectively, achieves the energy saving by 29.84%, 2.07%, and 68.80% on average to GA, GHO, and Lin.

Sophisticated Computation of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems

An embedded multiprocessor FPGA system can provide powerful and more functionalities than single processor system. However, the hardware-software partitioning problem is more complex in system design because the system components become escalation. In this paper, we propose a sophisticated computation method (SCM) to solve hardware-software partitioning issues for embedded multiprocessor FPGA systems. The SCM consists of two levels partition which includes processors-fit level and multi-fit level constraints. In processors-fit level, the partitioning results of unsatisfying processor constraint can be rapidly eliminated. Next, multi-fit level constraints compute various system constraints that based on divide-and-conquer and exhaust methods. Experimental results show that our proposed method can rapidly obtain better partitioning results.

An Integrated Functional Verification Tool for FPGA Systems

Hundreds of thousands circuits can not be verified easily while develop a field programmable gate array (FPGA) system. In this paper, we develop a functional verification tool, namely FVT, to verify the designer defined specification of functionalities with simulator and emulator in a FPGA system. In addition, FVT can point out the exact bugs for functionality where locates at specific cycle. Experiment results show that FVT can save time up to 99%.

A MULTI-BAND LOW NOISE AMPLIFIER WITH GAIN FLATNESS AND BANDWIDTH ENHANCEMENT

In this paper, a differential multi-band CMOS low noise amplifier (LNA) is proposed that is operated within a range of 1500–2700 MHz with input matching capacitor switching and gain flatness performance enhancement technique. Traditional multi-band LNAs have poor performances on gain flatness performance. Therefore, we propose a new multi-band LNA which obtain good gain flatness performance by integrating the characteristics of the transistor trans-conductance and LC resonant load. The new LNA can also achieve a tunable frequency at different matching capacitance conditions. The post-layout simulation results shows that the voltage gain is between 19.3 dB and 22.4 dB, the NF is less than 2.5 dB, and the 1-dB compression point is about -5.1 dBm. The LNA consumes 17.79 mW under 1.8 V supply voltage in TSMC 0.18-um RF CMOS process.

Middleware Software for Embedded Systems

Embedded systems with communicating and computing ability and multimedia functions work to every corner of daily life. However, the diverse architectures of embedded systems cause problems corresponding to reuse, portability and dependability. Middleware is a set of software that executes between operating system and application to solve stated problems. The advantages include unified interface, scalable and transparent abilities. This project investigates middleware technology on embedded systems and then proposes embedded middleware architecture to overcome the problems relating to reuse, portability, dependability and transparency. The proposed middleware consists of API module, service manager module and content manager module. The API module is designed to communicate with upper layer and lower layer by unified interface. Also, it provides a set of methods for solving problems of portability and dependability. The service manager module conducts a set of services for application. Moreover, it is able to automatically generate and deploy content information. The content manager module organizes and supplies information to the service manager module. Additionally, it solves transparent problem by ASCII and URL representation. In order to verify the feasibility for the proposed approach, we design the application of touch screen for embedded middleware system. Not only middleware but also embedded operating system, shell script, embedded graphical user interface and application are validated. Finally, we assess the functionality and integrated test of embedded middleware system by S3C2410 and XScale PXA270 system.

Efficient energy exploration for embedded systems

Mobile and ubiquitous computation of embedded system exacerbates energy consumption. In this work, we propose minimum energy path (MEP) approach to improve energy efficiency for embedded system. The MEP adopts path-based strategy to constructs a set of path class. Each path comprises the number of tasks that will be sequentially determined the role depending on the energy consumption. As a result, the energy efficiency is gradually improved while sequential paths are progressively identified the role of tasks. Experimental results show that MEP that can achieve 7.88% energy saving on average in all cases.

Grey decision of optimal simultaneous mapping and clustering to improve FPGA performance

This work studies how the architectural parameters of LUT-based field programmable gate arrays (FPGAs) are related to the LUT cluster size N and input number k A novel algorithm is proposed to combine grey decision-making approach for solving the problem of FPGA performance. Experimental results demonstrate that the algorithm improves the DAO map+T-VPack delay by 7.27% and reduces the SMAC total of CLB number by 22.15% on average. Furthermore, our proposed can get optimizes performance by appropriate selection of pairs of LUT cluster size N and input number k to construct the FPGA architecture with inequality demandable weight in area, energy, and delay.

RCGES: Retargetable Code Generation for Embedded Systems

With the integration of computer technology, consumer products, and communication facilities, the software in an embedded system now accounts for as much as 70% of total system functionalities. In this paper, we propose a code generation methodology called RCGES (Retargetable Code Generation for Embedded Systems) for the automatic code generation on retargetable embedded systems and two issues are solved. Firstly, an embedded C code for embedded processor is generated automatically from ANSI (American National Standards Institute) C code based specification using our proposed code generation algorithm. Secondly, we develop a graphical user interface to configure the parameter for retarget processor of embedded system. Two embedded system examples, 8051-based and PIC (Peripheral Interface Controller)-based, are used to illustrate the feasibility of the RCGES methodology.