Sandeep Kumar Samal

Design challenges and solutions for ultra-high-density monolithic 3D ICs

Monolithic 3D ICs (M3D) are an emerging technology that offers an ultra-high-density 3D integration due to the extremely small size of monolithic inter-tier vias. We explore various design styles available in M3D and present design techniques to obtain GDSII-level signoff quality results for each of these styles. We also discuss various challenges facing each style and provide solutions to them.

Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs

In this paper, we present a comprehensive study of the unique thermal behavior in monolithic 3D ICs. In particular, we study the impact of the thin inter-layer dielectric (ILD) between the device tiers on vertical thermal coupling. In addition, we develop a fast and accurate compact full-chip thermal analysis model based on non-linear regression technique. Our model is extremely fast and highly accurate with an error of less than 5%. This model is incorporated into a thermal-aware 3D-floorplanner that runs without significant runtime overhead. We observe up to 22% reduction in the maximum temperature with insignificant area and performance overhead.

Full chip impact study of power delivery network designs in monolithic 3D ICs

In this paper, we present a comprehensive study on the impact of power delivery network (PDN) on full-chip wirelength, routability, power, and thermal effects in monolithic 3D ICs. Our studies first show that the full PDN worsens routing congestion more severely in monolithic 3D ICs than in 2D designs due to the significant reduction in resources for 3D connections. The increase in signal wirelength translates into additional net switching power dissipation, which significantly contributes to total power. This in turn aggravates thermal issues in 3D ICs. In addition, we observe that PDN tradeoffs among wirelength, power, and thermal are more pronounced in monolithic 3D ICs than TSV-based 3D and 2D designs. This is because of the higher integration density and the severe competition between signal and power connections. Lastly, we develop various PDN design optimization techniques for monolithic 3D ICs and obtain up to 8% signal wirelength and 5% maximum temperature reduction under the given IR drop budget.

Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs

Power, performance, area, and cost analysis of TSV, mini-TSV, and monolithic 3D ICs is presented. Power savings for TSV, mini-TSV, and monolithic 3D ICs are 21%, 25%, and 37%, respectively, compared to that of a 2D IC. It is shown that monolithic 3D can deliver one node PPC benefit, whereas TSV 3D or mini-TSV 3D can only achieve a half node PPC advantage.

Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs

In this paper, we first present a comprehensive study of the unique thermal behavior in monolithic 3-D integrated circuits (ICs) in contrast to through silicon via-based 3-D ICs. In particular, we study the impact of the thin interlayer dielectric between the device tiers on vertical thermal coupling. We then study and compare the impact of different application-based package structures on the thermal behavior of monolithic 3-D ICs. With these unique properties and behavior, we develop a fast and accurate compact full-chip thermal analysis model based on nonlinear regression technique which adapts to the package structure during development and hence considers it during temperature evaluation. Our model is extremely fast and highly accurate with an error of less than 5%. This model is incorporated into a thermal-aware 3-D-floorplanner that runs without significant runtime overhead. We use the floorplanner with our package-aware thermal model and observe up to 22% reduction in the maximum temperature with insignificant area and performance overhead.

Ultralow Power Circuit Design With Subthreshold/Near-Threshold 3-D IC Technologies

The requirement of ultralow power and energy efficient systems is becoming more and more important with the increase in the use of miniaturized portable devices and unsupervised remote sensor systems. 3-D integration is an emerging technology that helps in reducing footprint as well as power. In this paper, we study in detail the combined benefits of 3-D ICs and low-voltage supply designs to obtain maximum energy efficiency. We implement different types of circuits in conventional 2-D and through-silicon-via-based 3-D designs at different supply voltages varying from nominal to subthreshold voltages. The impact of 3-D integration on these different types of circuits is analyzed. Our study is based on power and energy comparison of full GDSII layouts. Our study confirms that subthreshold/near-threshold circuits indeed offer a few orders of magnitude power versus performance tradeoff with further improvement due to 3-D implementation. In addition, 3-D designs reduce the footprint area up to 78% and wirelength up to 33% compared with the 2-D counterpart for individual design benchmarks. Our studies also show that thermal and IR drop issues are negligible in subthreshold 3-D implementation due to its extreme low-power operation. Finally, we demonstrate the low-power and high-memory bandwidth advantages of many-core 3-D subthreshold circuits.

Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs

In this paper, we present a comprehensive study on the impact of power delivery network (PDN) on full-chip wirelength, routability, power, and thermal effects in gate-level monolithic 3-D (M3-D) ICs across different technology nodes. Our studies show that PDN worsens routing congestion more severely in M3-D ICs than in 2-D designs due to the significant reduction in resources for 3-D connections. The relative impact worsens at advanced technology nodes due to higher congestion of interconnects. The increase in signal wirelength translates into additional net switching power dissipation, which significantly contributes to total power. This in turn aggravates thermal issues further in 3-D ICs. In addition, we observe that PDN tradeoffs among wirelength, power, and thermal are more pronounced in M3-D ICs than through silicon via-based 3-D and 2-D designs because of the higher integration density and the severe competition between signal and power connections. We also compare the impact of PDN on full chip routing in M3-D ICs versus face-to-face 3-D ICs. Lastly, we use various PDN design optimization techniques for M3-D ICs at different nodes and obtain up to 13.9% signal wirelength and 17.6% total power reduction under the given IR drop budget.

Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs

In this paper, we develop tier partitioning strategy to mitigate back-end-of-line (BEOL) interconnect delay degradation and cost issues in monolithic 3D ICs (M3D). First, we study the routing overhead and delay degradation caused by tungsten BEOL interconnect in the bottom-tier of M3D. Our study shows that tungsten BEOL reduces performance by up to 30% at 4× resistance increase of bottom-tier interconnect. In addition, the bottom-tier BEOL adds a routing overhead to 3D nets, which is neglected in the state-of-the-art flow. Next, we develop two partitioning methods targeted specifically towards BEOL impact reduction. Our path-based approach identifies critical timing paths and places their cells in the top-tier to reduce the impact of delay degradation and routing overhead. Our net-based partitioning methodology confines the nets with long 2D wirelength into the top-tier to reduce the overall routing demand, and hence the metal layer usage in the bottom-tier. This in turn results in BEOL cost savings. Using a foundry 22nm FDSOI technology and full-chip GDS designs, we achieve tolerance of up to 4× increase in the bottom-tier BEOL resistance using our partitioning strategy. In addition, we save up to 3 metal layers in the bottom-tier of our M3D designs with up to 32% power savings over 2D IC for an interconnect dominated benchmark.

Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology

In this paper, we conduct a comprehensive design comparison of 2D ICs, monolithic 3D ICs and TSV-based 3D ICs using a silicon-validated 14nm FinFET foundry technology and commercial quality designs. Through full-chip layouts and sign-off analysis using commercial-grade tools, the potential of monolithic 3D IC is explored and validated in terms of power, performance and area against that of TSV-based 3D ICs and 2D ICs.

Design Challenges and Solutions for Ultra-High-Density Monolithic 3D ICs

Monolithic 3D ICs (M3D) are an emerging technology that offers an ultra-high-density 3D integration due to the extremely small size of monolithic inter-tier vias. We explore various design styles available in M3D and present design techniques to obtain GDSII-level signoff quality results for each of these styles. We also discuss various challenges facing each style and provide solutions to them.