Shreepad Panth

3D-MAPS: 3D Massively parallel processor with stacked memory

Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration, but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM. Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5x5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.

Design and CAD methodologies for low power gate-level monolithic 3D ICs

In a gate-level monolithic 3D IC (M3D), all the transistors in a single logic gate occupy the same tier, and gates in different tiers are connected using nano-scale monolithic inter-tier vias. This design style has the benefit of the superior power-performance quality offered by flat implementations (unlike block-level M3D), and zero total silicon area overhead compared to 2D (unlike transistor-level M3D). In this paper we develop, for the first time, a complete RTL-to-GDSII design flow for gate-level M3D. Our tool flow is based on commercial tools built for 2D ICs and enhanced with our 3D-specific methodologies. We use this flow along with a 28nm PDK to build layouts for the OpenSPARC T2 core. Our simulations show that at the same performance, gate-level M3D offers 16% total power reduction with 0% area overhead compared to commercial quality 2D IC designs.

High-density integration of functional modules using monolithic 3D-IC technology

Three dimensional integrated circuits (3D-ICs) have emerged as a promising solution to continue device scaling. They can be realized using Through Silicon Vias (TSVs), or monolithic integration using Monolithic Inter-tier vias (MIVs), an emerging alternative that provides much higher via densities. In this paper, we provide a framework for floorplanning existing 2D IP blocks into 3D-ICs using MIVs. We take the floorplanning solution all the way through place-and-route and report post-layout metrics for area, wirelength, timing, and power consumption. Results show that the wirelength of TSV-based 3D designs outperform 2D designs by upto 14% in large-scale circuits only. MIV-based 3D designs, however, offer an average wirelength improvement of 33% for a wide range of benchmark circuits. We also show that while TSV-based 3D cannot improve the performance and power unless the TSV capacitance is reduced, MIV-based 3D offers significant reduction of upto 33% in the longest path delay and 35% in the inter-block net power.

Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations

In this paper we study the power vs. performance tradeoff in block-level monolithic 3D IC designs. Our study shows that we can close the power-performance gap between 2D and a theoretical lower bound by up to 50%. We model the inter-tier performance variations caused by a low temperature manufacturing process on the non-bottom tiers. We also model an alternate manufacturing process, where highly resistive tungsten interconnects are used on the bottom tier to withstand a high temperature process on the non bottom tiers. We propose a variation-aware floorplanning technique that makes our design more tolerant to these variations. We demonstrate that our design methods can help us obtain high quality designs even under inter-tier performance variations.

Design challenges and solutions for ultra-high-density monolithic 3D ICs

Monolithic 3D ICs (M3D) are an emerging technology that offers an ultra-high-density 3D integration due to the extremely small size of monolithic inter-tier vias. We explore various design styles available in M3D and present design techniques to obtain GDSII-level signoff quality results for each of these styles. We also discuss various challenges facing each style and provide solutions to them.

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)

This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 \microm-diameter, 6 \micro m-height through-silicon vias (TSVs) and 3.4\nbsp\microm-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.

Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs

Monolithic 3D (M3D) is an emerging technology that enables integration density which is orders of magnitude higher than that offered by through-silicon-vias. In this paper, we demonstrate that a modified 2D placement technique coupled with a post-placement partitioning step is sufficient to produce high-quality M3D placement solutions. We also present a commercial router-based monolithic intertier via insertion methodology that improves the routability of M3D ICs. We demonstrate that, unlike in 2D ICs, the routing supply and demand in M3D ICs are not completely independent of each other. We develop a routing demand model for M3D ICs, and use it to develop an

Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs

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Scan test of die logic in 3D ICs using TSV probing

min-overflow partitioner that enhances routability by off-loading demand from one tier to another. This technique reduces the routed wirelength and the power delay product by up to 7.44% and 4.31%, respectively. This allows a two-tier M3D IC to achieve, on average, 19.9% and 11.8% improvement in routed wirelength and power delay product over 2D, even with reduced metal layer usage.

Scan chain and power delivery network synthesis for pre-bond test of 3D ICs

In this paper, we present a comprehensive study of the unique thermal behavior in monolithic 3D ICs. In particular, we study the impact of the thin inter-layer dielectric (ILD) between the device tiers on vertical thermal coupling. In addition, we develop a fast and accurate compact full-chip thermal analysis model based on non-linear regression technique. Our model is extremely fast and highly accurate with an error of less than 5%. This model is incorporated into a thermal-aware 3D-floorplanner that runs without significant runtime overhead. We observe up to 22% reduction in the maximum temperature with insignificant area and performance overhead.