Uygar E. Avci

Tunnel Field-Effect Transistors: Prospects and Challenges

The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage (VDD). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at LG = 13 nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional VDD. Also, P-TFET current-drive is between 1× to 0.5× of N-TFET, depending on choice of IOFF and VDD. There are many challenges to realizing TFETs in products, such as the requirement of high quality III-V materials and oxides with very thin body dimensions, and the TFETs layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.

Bandgap engineering of group IV materials for complementary n and p tunneling field effect transistors

Direct bandgap transition engineering using stress, alloying, and quantum confinement is proposed to achieve high performing complementary n and p tunneling field effect transistors (TFETs) based on group IV materials. The critical tensile stress for this transition decreases in Ge1−xSnx for Sn content 0≤x≤0.068, calculated with the Nonlocal Empirical Pseudopotential method. Direct sub eV bandgap leads to high ON current in both n and p Ge and Ge1−xSnx TFETs, simulated using the sp3d5s*-SO model. Ge and Ge1−xSnx show an advantage over III-V p TFETs achieving steep subthreshold operation, which is limited in III-V devices by their low density of electron states.

The ultimate CMOS device and beyond

For the past 40 years, relentless focus on Moores Law transistor scaling has delivered ever-improving CMOS transistor density. This paper discusses architectural and materials options which will contribute to the ultimate CMOS device. In addition, the paper reviews device options beyond the ultimate CMOS device.

Integration of Back-Gate doping for 15-nm node floating body cell (FBC) memory

Key process features of a scaled, high-performance planar FBC memory fabricated on 25-nm undoped Si and 10-nm BOX SOI substrates are presented. Back-Gate (BG) doping process is revealed to be a critical part of the FBC integration. BG dopant loss due to oxidation and high-temperature processes is minimized to enable high performance at scaled diffusion widths (W<100 nm). Integrating BG doping processes and designing tips and source/drain, we demonstrate a memory retention of over 1 sec (@ 3-µA sensing window) in scaled cells (Lg=50 nm, W=85 nm) suitable for 15-nm technology node.

Floating Body Cell with Independently-Controlled Double Gates for High Density Memory

An aggressively scaled, self-aligned, independently controlled double-gate floating body cell (IDG FBC) is reported. This structure eases the scaling constraints of other FBC memory devices proposed to date. Enhanced memory performance has been demonstrated owing to the independent back gate with thin oxide and thin Si fin. Memory devices with 85-nm Lg and 30-nm fin widths (Z) have been shown to exhibit better memory characteristics at a lower voltage than alternative FBC structures at comparable dimensions. Design, fabrication, operation, and scalability of IDG FBC devices are discussed

A scaled floating body cell (FBC) memory with high-k+metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond

A scaled, undoped, thin-BOX, planar FBC technology is demonstrated for the first time, featuring 10-nm BOX, 25-nm SOI, high-k, metal gate, separate back-gate (BG) doping, and raised source-drain epitaxy. Retention of a minimum 3-muA sensing window for 100 ms, in devices with 60-nm gate-length (Lg) and 70-nm diffusion width (W), represents the best retention time of all sub-100-nm FBC devices. FBC scaling is predicted to be feasible at least to 40-nm Lg, enabling memory cell sizes much smaller than 6T-SRAM at 16-nm technology node. Functional 32-nm Lg devices suggest the feasibility at the 11-nm technology node.

Understanding the feasibility of scaled III–V TFET for logic by bridging atomistic simulations and experimental results

A detailed comparison between III-V TFETs experimental characteristics and atomistic quantum mechanical predictions is reported to study the validity of the performance improvement predictions of a scaled TFET. Simulations did not employ any fitting parameters to match the experimental data, but instead used material and geometry parameters as the only inputs. The results show that the experimental and simulation characteristics are in reasonable agreement, suggesting that the experimental devices are without significant unknown effects or defects, and the atomistic simulations have good predictability. The differences between scaled TFET predictions and large experimental TFET devices are shown to be due to the geometry, meaning that improved electrostatics with thin body and double-gate (DG) is required for TFET scaling. Results demonstrate that the III-V TFET is a realistic candidate for future low-voltage logic applications.

Heterojunction TFET Scaling and resonant-TFET for steep subthreshold slope at sub-9nm gate-length

The Tunneling Field Effect Transistor (TFET) is of interest for future low-power technologies due to its steep subthreshold-slope (SS) [1, 2]. In addition to understanding TFETs prospects for future technology nodes [3], we also need to assess if it enables continued scaling required for increasing transistor density. GaSb/InAs heterojunction TFET (Het-j TFET) is one of the leading TFET options due to its high drive-current [4]. In this paper, double-gate (DG) and nanowire (NW) Het-j TFETs (Fig. 1) are atomisticly modeled and compared to a MOSFET down to Lg~9nm, i.e. ITRS 2022 node [5]. To achieve TFET characteristics superior to a MOSFET, its DG body has to be extremely thin, so a NW TFET is therefore preferred due to its more relaxed thickness and better transistor characteristics. A new device - the Resonant-TFET (R-TFET), is proposed, with SS~25mV/dec over ~3.5 decades of current, enabling the scaling of tunneling transistors to sub-9nm gate-lengths (Lg).

Floating body cell (FBC) memory for 16-nm technology with low variation on thin silicon and 10-nm BOX

A scaled planar FBC technology with undoped-body is demonstrated featuring 10-nm BOX, 25-nm SOI, high-k and metal gate. Good agreement on retention window characteristics between measured data and simulations is achieved at multiple temperatures and illustrates Shockley-Read-Hall (SRH) recombination and generation dominated loss mechanism during hold condition. Optimization of Source-Drain (SD) and TIP implants are critical for achieving the balance between long retention time and large memory signal. For a minimum 3-muA sensing window, worst-case disturb retention of 25 ms is shown in scaled devices with 55 nm gate-length (LG) and 65 nm width (W). FBC scaling is predicted to be feasible at 16-nm technology node, enabling memory cell sizes much smaller than 6T-SRAM.

Floating-Body Diode—A Novel DRAM Device

A novel 8F2 DRAM cell is introduced, consisting of two gates controlling a low-doped silicon-on-insulator channel and opposite-polarity source and drain. Simulation with models calibrated to experimental floating-body cell data confirms virtual thyristor memory operation and demonstrates 85°C retention time in excess of 10 ms in a scaled FinFET architecture. With unit cell area comparable to that of conventional DRAM, 1.6-V total operation range, 1-ns program time, and CMOS-compatible process, floating-body diode is a candidate for stand-alone or embedded memory applications at 15-nm node and beyond.