Sandro Dalle Feste

New Architecture For An AES-EBU Digital Audio Receiver

This paper describes the realization of a digital audio receiver in accordance with the AES3 and S/PDIF format. It illustrates its realization and the performance obtained in terms of output jitter measured on the test chip. This receiver is realized in 3-metal layer 0.5 /spl mu/m CMOS technology, and with a 3.3 V power supply. This low power supply makes the interface compatible with the new generation of VLSI circuits, although it increases the analog design difficulties.

Smart System Case Studies

This chapter presents two case studies showing how the proposed approach applies to smart system design and optimization. The former is the virtual prototyping platform built for a laser pico-projector actuator, where MEMS, analog and digital components are simulated with the aim of optimizing the resulting image quality by means of firmware tuning. The latter, in the context of wearable equipment for inertial body motion reconstruction, deals with the modeling of an inertial sensor node, supporting system accuracy evaluation and sensor fusion enhancement. Finally, the Open-Source Test Case (OSTC) is described, showing a complete modeling and simulation flow on a publicly available design.

Mixed Mode Sigma-Delta ADC Design for High Quality Audio

The design of Sigma-Delta ADC embedded in large mixed analog and digital systems is critical especially when high quality audio performance must be retained. Idle tones reduction and noise modulation suppression can be achieved through proper architecture choice, building block design and careful layout.