Giovanni Cesura

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as EDGE (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme, etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or to reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-operability. This paper presents analog and digital base-band circuits that are able to support GSM (with EDGE), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) level.

A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC

This paper describes a fast digital background calibration algorithm for pipeline or cyclic analog-to-digital converters. The proposed method corrects for the finite gain/bandwidth of the interstage operational amplifier and for capacitor mismatch in multiplying digital-to-analog converters stages. The new algorithm, fast gain error correction, converges more than 100 times faster than other correlation-based correction techniques presented in literature. The high speed of convergence of the error estimation is due to the use of a polynomial interpolation that cancel the interference in the error estimation process caused by the input signal. This new method does not need any added analog circuitry, does not perturb the output samples, and requires only a digital finite-impulse response filter to implement the polynomial interpolation as opposed to existing fast converging correlation techniques.

A 6-10 bits Reconfigurable 20MS/s Digitally Enhanced Pipelined ADC for Multi-Standard Wireless Terminals

A 20MS/s pipelined ADC architecture can be reconfigured in 10 clock cycles to resolve 6, 8, 9 or 10 bits at maximum resolution. A 9.1bit ENOB and 74dB SFDR with a power consumption of only 8mW was achieved by using background digital calibration and op-amp sharing techniques. The test chip, containing two ADC for I and Q processing within a wireless receiver, has been realized in a 0.13mum pure CMOS technology and uses 3.2mm2 silicon area

An 80MHz 4/spl times/ oversampled cascaded /spl Delta//spl Sigma/-pipelined ADC with 75dB DR and 87dB SFDR

A 2/sup nd/-order 4b /spl Delta//spl Sigma/ modulator in cascade with a 9b pipeline clocked at 80MHz achieves 75dB DR, 74dB peak SNR and more than 87dB SFDR in a 10MHz bandwidth by means of background digital linearization and noise-cancellation algorithms. The 0.18/spl mu/m CMOS chip consumes 240mW including reference generator, digital decimator and correction logic.

Mixed Mode Sigma-Delta ADC Design for High Quality Audio

The design of Sigma-Delta ADC embedded in large mixed analog and digital systems is critical especially when high quality audio performance must be retained. Idle tones reduction and noise modulation suppression can be achieved through proper architecture choice, building block design and careful layout.