Ming-Zhang Kuo

A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC

We present a pulse latch with a measured Vccmin at the circuit of 0.42 V and pulse width of approximately 3 FO4-inverter delays. A wider operating window and reduced dependence on the input rise-time and PVT variations were obtained using a new pulse generator. A pulse in the new generator starts when its input crosses the switching level of its input gate, unlike in the classic text-book-style pulse-generator. An 8 to 10% improvement in power, performance, and area (PPA) of a typical digital SOC is observed when a group of pulse latches is driven by a distributed clock regenerator (DCR). The DCR has the new pulse generator at its input stage and provides pulse clocks to the pulse latches. Experimental results in a 28-nm HKMG process closely match SPICE simulations.

A 4-GHz universal high-frequency on-chip testing platform for IP validation

This paper describes an on-chip intellectual property (IP) testing platform, Universal High Frequency Test structure (UHFTs), which makes logic, memory, and analog / mixed-signal IPs at-speed testable in the same testing structure. Any functional testing pattern can be loaded from an external pattern generator or a tester through standard 5-pin JTAG interfaces operating at 10 MHz or below. The on-chip multichannel JTAG interface and elastic buffers convert an externally supplied pattern to an on-chip at-speed high-frequency pattern. The pattern can have address, data, and control fields. Each field is applied as input to a DUT in anyone of 16 available DUT sites, fully synchronized to the on-chip global clock. The output from the DUT is captured at-speed and stored in an output buffer. The content of the output buffer is read out to an external tester through the elastic-buffer and JTAG interfaces under a program control. UHFTs, implemented in TSMC 28-nm High Performance CMOS process, has been successfully used in digital, including ATPG, BIST, and vector-based tests with the capability of mixed-signal and analog tests. UHFTs have been designed with a frequency goal of 4 GHz in TSMC 28-nm CMOS process in the slow corner.

Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology

We describe custom 6R, 2/4W general-purpose register files (GRF) in an ASIC-based SOC implemented in a N28 CMOS technology, which has roughly a 2~3 X smaller area, 2 X faster speed, and 5 X lower power than a logic-synthesized version. Synthesized and custom GRFs also have a different read behavior from static and dynamic circuitry used, respectively. This is addressed by modifying a bypass control block. Hardware showed a DVFS window of 0.5 V @circuit, 130 MHz to 0.96 V, 3.2 GHz.

A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS

This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V VDD down to 10 MHz at 0.5V, meeting almost all of the Dynamic Voltage Frequency Scaling (DVFS) requirements of Level-1 (L1) caches of a digital microprocessor SOC. It uses an unmodified technology-supported 0.156um2 high-current (HC) SRAM cell. Innovative and carefully optimized circuit solutions provide the wide operating range measured in hardware. We also discuss two circuit improvements, a cross-coupled PMOS-pair for each bitline-pair with mux readout and an independently-controlled precharge-and-write driver (ICPW), which gives a wider DVFS operating window with reduced sensitivities to Process-Voltage-Temperature (PVT) variations. Improved SRAM macros with new circuits have been designed and laid out and their performance and area verified in simulation.

A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm 2 per MB

A fully-pipelined tile-able 1MB SRAM IP with a 0.127um2 cell in a HKMG 28nm bulk technology has an area of 1.39mm2/MB with 79.2% array efficiency. It operates with 2-cycle latency up to 1GHz. The no-repair hardware has a circuit limited yield of 99.92 and 53% at 100 and 850MHz, respectively with 0.75V VDD. A Data Retention Voltage of 0.42V has been measured.