Sang-Hye Chung

A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping

This paper presents a high resolution two-step gated-ring oscillator (TSGRO) time-to-digital converter (TDC) in an all digital phase-locked loop (ADPLL). TSGRO-TDC consists of a coarse step and a fine step gated-ring oscillator (GRO) TDC to achieve a high resolution. An edge aligner is used in the fine step GRO-TDC to enhance a first-order noise shaping property. A meta-stability free selection logic (MSFSL) is proposed in this paper which achieves low power and small area. In 0.13μm CMOS process, TSGRO-TDC has a 3ps raw resolution and first-order noise shaping.

An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme

For chip-to-chip parallel interfaces, maintaining low power consumption while achieving high aggregate bandwidth is the key trend. Forwarded-clock (FC) architecture is well suited to this trend because of the simple structure and inherent correlation of clock and data jitter [1]. Clock-recovery circuits consume a large portion of the I/O power. PLL/DLLs with a phase interpolator are widely used for the clock recovery circuits. However, they dissipate high power and jitter-tracking bandwidth (JTB) is low (PLL) or high (DLL), degrading the jitter correlation between data and clock. Recently, injection-locked oscillators (ILOs) have drawn much attention for the clock-recovery circuit of the FC interfaces due to their low power consumption [3-6]. By de-tuning the free-running frequency of an ILO, clock deskew can be performed and multiphase clocks can be generated without an additional multiphase generator. Also, ILOs can provide JTB of several hundred MHz, which is optimal for the FC interfaces in terms of the jitter correlation and BER [5].

A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS

In this paper, a data-jitter mixing (DJM) forwarded-clock receiver is proposed that achieves high jitter correlation between data and a clock for high speed and small power consumption. The first-stage injection-locked oscillator (ILO) filters out high-frequency clock jitter that loses the correlation due to a latency mismatch between data and the clock. Then, a data-jitter mixer in the second stage of the proposed receiver further increases the jitter correlation reduced by nonoptimal jitter filtering in ILO. Moreover, the DJM reduces power supply noise induced jitter from a clock distribution network, while the conventional jitter filter cannot track the high-frequency jitter because of filtering it out. A prototype receiver implemented in 1-V 65-nm CMOS process achieves 9.6 Gb/s with 1.22-mW/Gb/s in spite of a 1.92-ns latency mismatch between data and a clock.

A Quarter-Rate Forwarded Clock Receiver Based on ILO With Low Jitter Tracking Bandwidth Variation Using Phase Shifting Phenomenon in 65 nm CMOS

This paper presents a quarter-rate forwarded clock (FC) receiver based on an injection-locked oscillator (ILO) which exploits a phenomenon in which phases of the output clock are shifted by the duty-cycle of an injection clock. Also, this paper describes the principle of this phase shifting phenomenon. To utilize the phase shifting phenomenon, a simple duty-cycle adjuster (DCA) is proposed. By using the DCA, the proposed FC receiver achieves 760 MHz of wide jitter tracking bandwidth (JTB) and 60 MHz JTB variation in spite of clock deskew. The proposed receiver achieves a 12 Gb/s data rate with 0.92 mW/Gb/s in a 1 V 65 nm CMOS process.

1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS

This paper presents a data jitter mixing forwarded-clock receiver which is robust against power supply induced jitter (PSIJ) and overcomes 1.92ns latency mismatch between data and clock. The forwarded-clock architecture has a tradeoff between the number of clock channels and the achievable data rate due to the lack of the jitter correlation between data and clock. Moreover, PSIJ due to a long clock distribution network and an injection-locked oscillator reduces the jitter correlation further. The proposed receiver eases this tradeoff, and also increases the jitter correlation reduced by PSIJ. The test chip achieves 9.6Gb/s with 1.22mW/Gb/s and occupies only 0.017mm2 in 65nm CMOS.

Area-efficient dynamic thermal management unit using MDLL with shared DLL scheme for many-core processors

An area-efficient dynamic thermal management (DTM) unit using multiplying delay-locked loop (MDLL) with shared DLL scheme is proposed for per-core DTM in many-core processors. The proposed DTM unit consists of a MDLL and a shared-DLL-based temperature sensor. The shared DLL takes part in both temperature sensing and frequency scaling while reducing the size of whole DTM unit. The area is reduced by 54.4% compared to the design in which a phase-locked loop (PLL) is used without any optimization scheme.

A Mobile 3-D Display Processor With A Bandwidth-Saving Subdivider

A mobile 3-D display processor with a subdivider is presented for higher visual quality on handhelds. By combining a subdivision technique with a 3-D display, the processor can support viewers see realistic smooth surfaces in the air. However, both the subdivision and the 3-D display processes require a high number of memory operations to mobile memory architecture. Therefore, we make efforts to save the bandwidth between the processor and off-chip memory. In the subdivider, we propose a recomputing based depth-first scheme that has much smaller working set than prior works. The proposed scheme achieves about 100:1 bandwidth reduction over the prior subdivision methods. Also the designed 3-D display engine reduces the bandwidth to 27% by reordering the operation sequence of the 3-D display process. This bandwidth saving translates into reductions of off-chip access energy and time. Consequently the overall bandwidth of both the subdivision and the 3-D display processes is affordable to a commercial mobile bus. In addition to saving bandwidth, our work provides enough visual quality and performance. Overall the 3-D display engine achieves 325 fps for 480×320 display resolution.

A Forwarded Clock Receiver Based on Injection-Locked Oscillator With AC-Coupled Clock Multiplication Unit in

This brief presents a forwarded clock receiver based on an injection-locked oscillator with a simple clock multiplication unit (CMU) to reduce the clock jitter and power consumption of the CMU. In addition, an optimal clock multiplication factor is considered to optimally multiply the clock frequency without serious degradation of the jitter correlation between data and clock. The proposed CMU employs ac coupling and a superposition technique to generate first-harmonic injection pulses. The measured power efficiency of the proposed receiver is 1.69 mW/Gb/s at a 7.4-Gb/s data rate in a 1.2 V 0.13-μm CMOS process.

0.13~\boldsymbol {\mu }

A source synchronous architecture with constant and wide jitter-tracking bandwidth (JTB) is presented. The proposed receiver is based on an injection-locked oscillator (ILO), which provides jitter filtering and phase deskew simultaneously. While using only the ILO has intrinsic two dependence problems (JTB versus deskew and JTB versus a voltage-controlled oscillator tuning range required for 1 unit interval deskew), the proposed receiver makes them independent. Therefore, the proposed receiver can achieve the optimal JTB in a wide range supporting various applications by controlling deskew phase and JTB independently. A test chip was implemented to prove 11-Gb/s data recovery with constant 70-MHz to 1-GHz JTB in 0.13-μm CMOS.

m CMOS

This paper presents a forwarded clock receiver based on an injection-locked oscillator (ILO) with a simple clock multiplication unit to reduce the clock jitter and power consumption. The clock multiplication unit employs AC coupling and superposition technique to generate first-harmonic pulses. The first-harmonic injection reduces the rms and peak to peak jitter of the ILO output clock by about 0.65ps (29%) and 46.06ps (65%), respectively. The measured power efficiency of the receiver is 1.69mW/Gbps at 7.4Gb/s data rate in a 1.2V 0.13µm CMOS process.