Sang-Hyun Joo
Samsung
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Publication
Featured researches published by Sang-Hyun Joo.
international solid-state circuits conference | 2012
Dae-Yeal Lee; Ik Joon Chang; Sangyong Yoon; Joon-Suc Jang; Dong-Su Jang; Wook-ghee Hahn; Jong-Yeol Park; Doo-gon Kim; Chi-Weon Yoon; Bong-Soon Lim; Byung-Jun Min; Sung-Won Yun; Ji-Sang Lee; Il-Han Park; K. Kim; Jeong-Yun Yun; Y. Kim; Yongsung Cho; Kyung-Min Kang; Sang-Hyun Joo; Jin-Young Chun; Jung-No Im; Seunghyuk Kwon; Seokjun Ham; An-Soo Park; Jae-Duk Yu; Nam-Hee Lee; Taesung Lee; Moosung Kim; Hoo-Sung Kim
The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].
international solid-state circuits conference | 2015
Jaewoo Im; Woopyo Jeong; Doohyun Kim; Sang-Wan Nam; Dongkyo Shim; Myung-Hoon Choi; Hyun-Jun Yoon; Dae-Han Kim; Y. Kim; Hyun Wook Park; Donghun Kwak; Sang-Won Park; Seok-Min Yoon; Wook-ghee Hahn; Jinho Ryu; Sang-Won Shim; Kyung-Tae Kang; Sung-Ho Choi; Jeong-Don Ihm; Young-Sun Min; In-Mo Kim; Doo-Sub Lee; Ji-Ho Cho; Oh-Suk Kwon; Ji-Sang Lee; Moosung Kim; Sang-Hyun Joo; Jae-Hoon Jang; Sang-Won Hwang; Dae-Seok Byeon
Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].
Society for Information Display. International Symposium (1999 : San Jose, Calif.). Proceedings | 1999
Hyeong-Jun Kim; D. H. Kim; Jun Haeng Lee; Il-gon Kim; G. S. Moon; J. H. Huh; J. W. Hwang; Sang-Hyun Joo; K. W. Kim; Jun H. Souk
A 7-inch full-color low-temperature poly-Si TFT-LCD with fully integrated driver circuits has been developed. Employing a novel LDD structure in the CMOS integrated drivers, highly stable devices have been attained. It was designed to provide various types of images, such as full, cinema, normal, and wide mode. The 7-inch TFTLCD is applicable for the car-navigation system or PDA applications.
Archive | 2011
Ki Hwan Choi; Sung Soo Lee; Jae-Woo Park; Sang-Hyun Joo
Archive | 2011
Ji-Sang Lee; Joon-Suc Jang; Sang-Hyun Joo
Archive | 2015
Sang-Hyun Joo
Archive | 2012
Sang-Hyun Joo; Ki Hwan Choi; Moo Sung Kim
Archive | 2014
Sang-Hyun Joo; Ki-whan Song; Ju Seok Lee; Kihwan Choi
Archive | 2012
Sang-Hyun Joo; Kitae Park; Sangyong Yoon; Jaeyong Jeong
Archive | 2014
K. Kim; Goeun Jung; Sang-Hyun Joo; Kye-Hyun Kyung
