Ki-whan Song

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

In mobile systems, the demand for the energy saving continues to require a low power memory sub-system. During the last decade, the floating-gate flash memory has been an indispensable low power memory solution. However, NOR flash memory has begun to show difficulties in scaling due to the devices reliability and yield issues. Over the past few years, phase-change random access memory (PRAM) has emerged as an alternative non-volatile memory (NVM) owing to its promising scalability and low cost process [1,2]. In this paper, a PRAM, implemented in a 58nm PRAM process with a low power double-data-rate nonvolatile memory (LPDDR2-N) interface, is presented [3].

A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniques

A 1.5-V 512-Mb DDR3 Synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and C IO minimization, which were achieved by on-die-termination (ODT)-merged output drivers, SCR type ESD protection, and self-calibration scheme. The hybrid latency control scheme can turn the DLL off in standby mode, reducing power consumption. User-friendly functions such as temperature read-out from on-chip sensor and per-bank-refresh were also implemented.

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology

The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].

A 31 ns Random Cycle VCAT-Based 4F

A functional 4F2 DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with more than twice turn-on current compared with the conventional recessed channel access transistor (RCAT). A new design methodology has been applied to accommodate 4F2 cell array, achieving both high performance and manufacturability. Especially, core block restructuring, word line (WL) strapping and hybrid bit line (BL) sense-amplifier (SA) scheme play an important role for enhancing AC performance and cell efficiency. A 50 Mb test chip was fabricated by 80 nm design rule and the measured random cycle time (tRC) and read latency (tRCD) are 31 ns and 8 ns, respectively. The median retention time for 88 Kb sample array is about 30 s at 90°C under dynamic operations. The core array size is reduced by 29% compared with conventional 6F2 DRAM.

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As device technology is scaling down, Vths of NAND flash cell show a wide distribution due to process variations such as random dopant fluctuation, etc. Since the extension of Vth distribution is directly related to degradation of program performance of NAND flash, it is more challenging to meet the market requirements for applications such as solid-state drivers (SSD). This paper presents a novel program scheme, called Adaptive Multi-pulse Program (AMP), for the scaled multi-bit/cell NAND flash devices. In the proposed program scheme memory cells are classified into several groups based on their own program speeds. F-N tunneling characteristic of NAND cell array is considered in determining the level of program bias for each group. Adaptive program pulses are applied to the predefined groups so that cells reach their target verify level at the same time, regardless of the difference of their program speed. Our experimental results show that AMP achieves 20% improvement on program performance due to the reduction of the number of verify executions by 39% in 3-bit/cell architecture NAND flash memory of 21 nm CMOS technology.

DRAM With Manufacturability and Enhanced Cell Efficiency

New 4F2 cell structure of VPT for the future DRAM devices has been successfully developed by using 30nm process technology. The VPT shows superior current driving capability of 33μA and steep subthreshold slope of 77mV/dec. The VPT device demonstrates excellent retention characteristics in static mode. The floating body effects can be reduced by adopting the gradual junction profile even in a pillar-type channel. Also, the VPT produces about 60% and 30% more gross dies per wafer than conventional 8F2 and 6F2 cells.

Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH

We present a new field effect mechanism on IGIDL in NAND flash strings. According to the proposed 5-terminal GIDL model, special care should be taken to optimize the biasing levels of inhibit scheme. Suggested incremental biasing scheme can be one of the solutions for reducing critical field that enhances boosting efficiency and maximizes memory yields.

Novel 4F 2 DRAM cell with Vertical Pillar Transistor(VPT)

As device technology is scaling down, Vths of NAND flash cell show a wide distribution due to process variations such as random dopant fluctuation, etc. Since the extension of Vth distribution is directly related to degradation of program performance of NAND flash, it is more challenging to meet the market requirements for applications such as solid-state drivers (SSD). This paper presents a novel program scheme, called Adaptive Multi-pulse Program (AMP), for the scaled multi-bit/cell NAND flash devices. In the proposed program scheme memory cells are classified into several groups based on their own program speeds. F-N tunneling characteristic of NAND cell array is considered in determining the level of program bias for each group. Adaptive program pulses are applied to the predefined groups so that cells reach their target verify level at the same time, regardless of the difference of their program speed. Our experimental results show that AMP achieves 20% improvement on program performance due to the reduction of the number of verify executions by 39% in 3-bit/cell architecture NAND flash memory of 21 nm CMOS technology.

A new GIDL phenomenon by field effect of neighboring cell transistors and its control solutions in sub-30 nm NAND flash devices

This paper introduces a novel silicon controlled rectifier (SCR)-based circuit. The proposed device using 70nm DRAM process obtained the high holding and low triggering voltages by using variable IR drop. These characteristics enable to discharge electrostatic discharge (ESD) current and ensure latch-up immunity for normal operations. Also, the proposed scheme is easily implemented through the modification of the metal connection compare to the conventional SCR-based device. We investigated electrical characteristics by both measurements and TCAD simulations. Measurement results showed the proposed SCR had triggering voltage of 6.2V, holding voltage of 3.3V, and the second breakdown current of 58mA/@mm.

Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell NAND FLASH

Multimedia and multi-tasking computing systems demand high bandwidth and multi-bank DRAMs. To meet these requirements, several challenges regarding the chip size penalty and noise concerns associated with multi-I/O lines should be resolved. This paper describes a 2.5-V, 288-Mb DRAM with a 32-bank architecture achieving a peak bandwidth of 2.0 GB/s using both 500-MHz differential clocks and 18-I/O organization. This chip features (1) an area- and performance-efficient chip architecture with well-mixed high-speed interface circuits with DRAM peripheral circuits to increase the cell efficiency, (2) a multi-level controlled equalizing scheme and a distributed sense amplifier-driving scheme to enhance the DRAM core timing margin while digressing from the conventional sub-wordline driving scheme, having 352 cells per sub-wordline, (3) an area-efficient column redundancy scheme with multiple fuse-boxes instead of excessive spare memory cell arrays for the multi-I/O architecture, (4) a zero-DC current receiver with a counter kick-back coupling scheme to reduce the reference coupling noise, and (5) a PVT (power, voltage, time) insensitive current control scheme.