Sang-hyun Lee

A New Cost-Effective Current-Balancing Multi-Channel LED Driver for a Large Screen LCD Backlight Units

A new current-balancing multi-channel LED driver is proposed in this paper. The conventional LED driver system consists of three cascaded power conversion stages and its driver stage has the same number of expensive boost converters as those of the LED channels. On the other hand, the proposed LED driver system consists of two cascaded power stages and its driver stage requires only passive devices instead of expensive boost converters. Nevertheless, all of the currents through multi-channel LEDs can be well balanced. Therefore, it features a smaller system size, improved efficiency, and lower cost. To confirm the validity of the proposed driver, its operation and performance are verified on a prototype for a 46” LCD TV.

Current degradation mechanism of single wall carbon nanotube emitters during field emission

Electron emission current degradation is often observed from printed single wall carbon nanotube emitters during field emission process. After a highly imposed emission, structural deformation of emitters from thin crystalline nanotube bundle to thick amorphous-type carbon fiber was observed. This deformation seems to relate to the current degradation, deteriorating the efficiency of field emission either by increasing the resistance of emitters or by decreasing the field enhancement factor of emitter tips. Two possible mechanisms of structural deformation are internal structural transformation by Joule heating under excessively imposed emission current and continuous adsorption of carbon particles on actively working emitters.

8.7 Physically unclonable function for secure key generation with a key error rate of 2E-38 in 45nm smart-card chips

Physically unclonable function (PUF) circuits are for generating unique secure keys or chip IDs based on intrinsic properties of each chip itself [1-2]. PUFs are a step forward to improve the security level compared to traditional NVM (non-volatile memory) solutions (FUSEs, EEPROM/FLASH, etc.) because they resolve security issues, such as active data-probing, transferring the security key from outside, etc. Since the MOSFET mismatch (e.g. size, doping concentration, mobility and oxide thickness) due to process variations cannot be fully controlled, PUFs, which are based on such phenomena, cannot be replicated. Unfortunately, the PUF output is erroneous by nature, as caused by thermal noise, voltage/temperature influence, aging effects, etc. The stability issue must be overcome since standard security applications, such as data encryption and digital signatures, have zero error-tolerance. In this work, a PUF structure based on the threshold voltage (Vth) difference of inverting logic gates is presented, which is implemented for secure 24b key generation in a 45nm smart card chip. The key is used as part of an encryption key and achieves an error rate as low as 2.01×10-38. The PUF system is also scalable for a larger key size.

Improvement of field emission characteristics of carbon nanotubes through metal layer intermediation

A method of fabricating carbon nanotube (CNT)-based field emitters has been studied to improve field emission characteristics. From the supplementary substrate coated with CNTs, CNTs were transferred to the objective substrate through the metal intermediation (MI) layer where the heat and pressure were applied. CNTs were vertically aligned on the objective substrate after removing the supplementary substrate. The field enhancement effect of emitters can be increased by the formation of the sharp edges through CNT transfer process. This MI process allows one to lower the processing temperature below 300 °C and form the patterned CNT emitter arrays.

A study on Driving of 35W(T5) fluorescent lamp by the electronic ballast using piezoelectric transformer

Recently, 35 W class Fluorescent lamps with 32 mm tube diameter are replaced with 32 W one with 26 mm in diameter to conserve lamp materials and to increase luminance efficiency. Moreover, 35, 28 and 14 W fluorescent lamps with 16 mm (T5) in diameter, which are nowadays developed, also may replace 32 W lamps again. Application of slim lamps, however, requires small sized electronic ballast to full fill the design philosophy of miniaturizing. However, the traditional magnetic ballasts operated at 50-60 Hz have been suffered from noticeable flicker, high loss, large crest factor and heavy weight. In this study, in order to solve these problems, a new type of electronic ballast, which is composed of rectifier, active power factor corrector, series resonant half bridge inverter and piezoelectric transformer, was proposed for driving T5 fluorescent lamp. Driving of piezoelectric transformer was carried out with input region for the ring electrode and output region for the dot electrode. A 35 W (T5) fluorescent lamp is successfully driven by the fabricated ballast with piezoelectric transformer. After driving the lamp using the proposed electronic ballast for 20 min, the input power factor and efficiency of ballast shown 0.95 and 86%, respectively, at operating frequency of 81 kHz. And also, the output power and temperature rise of piezoelectric transformer showed 35.07 W and 20.5 degC, respectively.

Voltage Clamped Tapped-Inductor Boost Converter with High Voltage Conversion Ratio

In this paper, voltage clamped tapped-inductor boost converter with high voltage conversion ratio is proposed. The conventional tapped-inductor boost converter has a serious drawback such as high voltage stresses across all power semiconductors due to the high resonant voltage caused by the leakage inductor of tapped inductor. Therefore, the dissipative snubber is essential for absorbing this resonant voltage, which could degrade the overall power conversion efficiency. To overcome these drawbacks, the proposed converter employs a voltage clamping capacitor instead of the dissipative snubber. Therefore, the voltage stresses of all power semiconductors are not only clamped as the output voltage but the power conversion efficiency can also be considerably improved. Moreover, since the energy stored in the clamp capacitor is transferred to the output side together with the input energy, the proposed converter can achieve the higher voltage conversion ratio than the conventional tapped-inductor boost converter. Therefore, the proposed converter is expected to be well suited to various applications demanding the high efficiency and high voltage conversion ratio. To confirm the validity of the proposed circuit, the theoretical analysis and experimental results of the proposed converter are presented.

The abnormality in gate oxide failure induced by stress-enhanced diffusion of polycrystalline silicon

Abstract An abnormal gate oxide failure was found in DRAM using deep submicron technology. Contrary to the general dielectric extrinsic breakdown, the degradation of gate oxide integrity was shown only in the gate lines of a small dimension, not in those of a large dimension. This abnormal oxide breakdown is due to the voids in the polycrystalline silicon, which are at the center of gate line with a small dimension. These voids are formed by both chemical potential difference and stress enhanced diffusion of polycrystalline silicon. The suppression method of these voids using sufficient source of polycrystalline silicon is proposed.

23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller

Although the LPDDR4 interface has enabled industry requirements, such as low power consumption and high bandwidth, additional evolution of the current LPDDR4 performance is expected. To respond to the need for more power efficient devices with higher bandwidth, a 2nd generation LPDDR4 (referred to as LPDDR4X), with extreme low power and extended performance, has been developed in this work. In the controller, the output drivers for data signal (DQ) and data strobe signal (DQS) dominate the power consumption. An efficient method to reduce the output driver power is to reduce the supply voltage (VDDQ) [1]. A low voltage-swing terminated logic (LVSTL) [2] can support this solution by changing the operation region of the pull-up NMOS transistor from the saturation region to the triode region. However, another power supply whose minimum value is VTH_NMOS+VDDQ is required for the pull-up NMOS transistor to serve as source-series termination. In this work, P-over-N topology replaces LVSTL and allows for the use of a single VDDQ (0.6V), thus reducing pre-driver power. Another major improvement in the proposed LPDDR4X controller is that it has functions to compensate for the large variation of DQS output transition time from CK (ΔtDQSCK) [3] due to the lack of a delay locked loop (DLL) in LPDDR4 DRAM [4]. Furthermore, the reference voltage on DRAM and the duty cycle of both DQ and DQS are initially calibrated to increase the valid window margin (VWM) during write operations. VWM is the time interval where all DQs remain valid before and after DQS edge in order to capture DQs correctly.

A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization

This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit with an asynchronous baud-rate sampling to achieve an adaptive equalization as well as a data rate acquisition. The proposed scheme also enables the use of a successive approximation register (SAR) based approach in the frequency acquisition and results in a fast coarse lock process. The CDR guarantees a robust operation of a fine locking even in the presence of large input data jitter due to the adaptive equalization and a jitter-tolerable rotation frequency detector (RFD) that eliminates a dead-zone problem with a simple circuitry. The fabricated CDR in 65 nm CMOS shows a wide lock range of 0.65-to-10.5 Gb/s at a bit error rate (BER) of 10-12. The CDR consumes 26 mW from a single supply voltage of 1 V at 10 Gb/s including the power consumption for equalizer. By an adaptive current bias control, the power consumption is also linearly scaled down with the data rate, exhibiting a slope of about 2 mW decrease per Gb/s.

A wide-range frequency tunable SMR-CMOS oscillator for gas sensing

Precise-frequency tunability over a wide-range plays an important role in the SMR (solidly mounted resonators) CMOS oscillator circuit. Although commercially available network analyzers have been the standard for highly sensitive mass sensing using SMR, it is not possible to miniaturize it for mobile sensor. In this work, the wide-range of resonance frequency is tuned by changing the number of inverter chains. The effect of inverter chains for the device sensitivity is also investigated. We also show capacitors used for starting a resonance play an important role in the device sensitivity. We believe this technique will be an essential platform for one-chip SMR-CMOS gas sensor having different resonance frequencies due to the selection of piezoelectric materials or the process variation during the fabrication.