Du-Heon Song

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

A monolithic 64 Gb MLC NAND flash based on 21 nm process technology has been developed. The device consists of 4-plane arrays and provides page size of up to 32 KB. It also features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s. To improve performance and reliability, on-chip randomizer, soft data readout, and incremental bit line pre-charge scheme have been developed.

Charge trapping induced DRAM data retention time degradation under wafer-level burn-in stress

This paper investigates the effects of wafer burn-in on the degradation of DRAM data retention time characteristics. The problem was characterized using a substrate electron injection method described in this paper. As a result, it could be experimentally demonstrated that the data retention time degradation was attributed to the enhanced GIDL (gate induced drain leakage) due to the increased electric field caused by electron trapping in the gate oxide during wafer burn-in stress.

A new approach for trap analysis of vertical NAND flash cell using RTN characteristics

We introduce new phenomena that show turn-on at back-side for Vertical NAND (V-NAND) with back-insulator and propose a new method to analyze the trap of back-interface related to the phenomena. Back-side traps have been analyzed with the back-gate structure [1]. However, V-NAND has no back-gate structure, so its difficult to observe traps. With RTN method we proposed, its possible for us to observe back-side traps.

Evaluation of STI degradation causing DRAM standby current failure in burn-in mode operation using a carrier injection method

P+ to p+ isolation degradation that causes DRAM standby current failure under burn-in mode operation is investigated. Although the isolation of the test devices dose not show any degradation or weakness in conventional electrical characterization, it is found that the degradation can be observed by a carrier injection method. Using the simple carrier injection method to simulate the real operating condition of a DRAM chip, a potential problem of the isolation degradation can be easily found, which cannot be screened by conventional electrical measurement.

Hot hole-induced device degradation by drain junction reverse current

Abstract In this paper, device degradation mechanisms by drain junction reverse current in the off-state were studied, using n-type metal–oxide–semiconductor field-effect transistor (N-MOSFET), which is used as the high-voltage core circuit of flash memory chip. Components of drain leakage currents in the off-state are gate-induced drain-leakage (GIDL) and drain junction reverse currents. Device degradation phenomenon and mechanism by GIDL in the MOSFETs have been well known, but those by drain junction reverse current have not. A variety of measurement conditions for separating drain junction reverse current from total drain current in the off-state were suggested, and hole injection phenomenon into the gate was investigated through the modified capacitive-voltage method. In addition, we investigated the location of electron–hole generation between GIDL and drain junction reverse current through the lateral profile of trapped hole extracted from charge pumping method.

A Study of High-Voltage p-Type MOSFET Degradation Under AC Stress

In this paper, the degradation characteristics of high-voltage (HV) p-type MOSFETs are investigated during negative unipolar ac stress on the gate electrode. The threshold voltage under ac stress is shifted gradually by both the negative-bias temperature-instability mechanism and Fowler-Nordheim degradation. We qualitatively analyze the degradation characteristics of HV p-type MOSFETs under ac stress, and observe the threshold voltage saturation for HV p-type MOSFETs at long ac stress. Based on the effects of temperature and duty cycles, we offer a suitable model of degradation saturation after long ac stress, which is caused by interface trap saturation and recovery during pulse delay timing, which is dependent on thermal activation energy.

Abnormal degradation of high-voltage p-type MOSFET with n+ polycrystalline silicon gate during AC stress

We investigated the abnormal degradation of high-voltage p-type MOSFET (HV pMOSFET) under negative AC gate bias stress. In HV pMOSFET with n+ polycrystalline silicon (poly-Si) gate, the abnormal degradation occurs after the gradual degradation during negative AC stress. The abnormal degradation is suppressed by changing the gate material from n+ poly-Si to p+ poly-Si, and it is caused by hot holes produced by the impact ionization near the surface when electrons move from the gate toward the gate oxide. We suggest a possible mechanism to explain the improvement of degradation by using p+ poly-Si as a gate material.

Lateral-Extended (LatEx.) active for improvement of data retention time for sub 60nm DRAM era

A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data retention time enhancement was successfully achieved in 60 nm technology node DRAM by virtue of reduced source/drain area and improved subthreshold slope due to decreased cross-sectional area of top trench profile and vertical bottom trench process. In this paper, LatEx active coupled with SRCAT is proved to be suitable for sub 60 nm DRAM cell array transistor technology.

Comments on "A numerical analysis of the storage times of dynamic random-access memory cells incorporating ultrathin dielectrics"

This correspondence discusses two practical aspects which have to be included in the storage time analysis of the above referenced paper. First of all, the value of the diffusion current is overestimated by three orders of magnitude in calculating the log time dependence. Secondly, in the total junction leakage current, the generation current near the edges of the n -Si/SiO interface is a more important factor than the bulk gen- eration current. Inclusion of those two practical aspects could lead to a different prediction of storage times in future DRAM cells with thin di- electrics. Index Terms—Dram, leakage currents, storage times, ultrathin di- electrics. Rapid reduction of the cell size of modern dynamic random access memories (DRAMs) requires continuous decrease of the dielectric thickness. The leakage current of such thin dielectrics will soon be- come an important factor in determining the storage time of DRAM cells and the analysis technique including dielectric leakage currents is an urgent issue in DRAM cell design. The numerical analysis technique presented in the above paper (1) includes a complete set of dielectric leakage mechanisms and therefore is an important contribution to its field. However, even in DRAM cells with thin dielectrics, the junction leakage current still plays an important role in the total leakage current and it is essential to evaluate the exact amount of the junction leakage current (2), (3). The junction leakage current in the DRAM cell is composed of three components as shown in (1); the diffusion current , the bulk generation current (4), and the generation current near the edge of the n -Si/SiO interface (the surface generation current, ) (5).