Sang-il Jung

Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)

The operational six-transistor SRAM cell was experimentally demonstrated using bulk FinFET CMOS technology. A cell size of 0.79 /spl mu/m/sup 2/ was achieved by 90 nm node technology, with stable operation at 1.2 V using 4 levels of W and Al interconnects. Static noise margin of 280 mV was obtained at V/sub cc/ of 1.2 V. To our knowledge, this represents the first experimental demonstration of a fully integrated bulk FinFET SRAM cell.

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.

An all pixel PDAF CMOS image sensor with 0.64μmx1.28μm photodiode separated by self-aligned in-pixel deep trench isolation for high AF performance

We present a CMOS image sensor (CIS) with phase detection auto-focus (PDAF) in all pixels. The size of photodiode (PD) is 0.64μm by 1.28μm, the smallest ever reported and two PDs compose a single pixel. Inter PD isolation was fabricated by deep trench isolation (DTI) process in order to obtain an accurate AF performance. The layout and depth of DTI was optimized in order to eliminate side effects and maximize the performance even at extremely low light condition up to 1lux. In particular the AF performance remains comparable to that of 0.70μm dual PD CIS. By using our unique technology, it seems plausible to scale further down the size of pixels in dual PD CIS without sacrificing AF performance.

10nm 2 nd generation BEOL technology with optimized illumination and LELELELE

10nm 2nd generation BEOL technology is described with an optimized illumination system and multi-patterning lithography. While the optimized illumination system offered a possibility to pattern reduced metal pitches in the preferred orientation, difficulties of T-T and T-S patterning still remained. It was overcome by increasing the number of available multi-patterning colors from 2 to 4. First-ever implementation of LELELELE with tight inter-color misalignment control increased scalability up to 17.1% and was demonstrated with SRAM 128Mb yield.

Advanced image sensor technology for pixel scaling down toward 1.0µm (Invited)

As pixel size of image sensors shrinks down rapidly, we are reaching technical barrier to get the required low light performance. In this paper, recent advanced technologies such as backside illumination, new color filter array, low F-number with extended depth of field technologies, etc. are introduced to overcome such a barrier. It is shown that the integration of these advanced sensor technologies can make pixel size shrink down toward 1.0 mum with the required performance.