Duck-Hyung Lee

Extranodal NK / T‐cell lymphoma with cutaneous involvement: ‘nasal’ vs. ‘nasal‐type’ subgroups— a retrospective study of 18 patients

Background  Extranodal natural killer T (NK/T) cell lymphoma is subcategorized into ‘nasal’ and ‘nasal‐type’ NK/T‐cell lymphomas according to the primary sites of anatomical involvement.

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

Application of Plasma-Doping (PLAD) Technique to Reduce Dark Current of CMOS Image Sensors

Plasma doping (PLAD) was applied to reduce the dark current of CMOS image sensor (CIS), for the first time. PLAD was employed around shallow trench isolation (STI) to screen the defective sidewalls and edges of STI from the depletion region of photodiode. This technique can provide not only shallow but also conformal doping around the STI, making it a suitable doping technique for pinning purposes for CISs with sub-2-mum pixel pitch. The measured results show that temporal noise and dark signal deviation as well as dark level decrease

Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)

The operational six-transistor SRAM cell was experimentally demonstrated using bulk FinFET CMOS technology. A cell size of 0.79 /spl mu/m/sup 2/ was achieved by 90 nm node technology, with stable operation at 1.2 V using 4 levels of W and Al interconnects. Static noise margin of 280 mV was obtained at V/sub cc/ of 1.2 V. To our knowledge, this represents the first experimental demonstration of a fully integrated bulk FinFET SRAM cell.

Novel Charge Trap Devices with NCBO Trap Layers for NVM or Image Sensor

ZnO or AlxGa1-xN charge trap device showed large memory window (>7V) with fast P/E speed (plusmn17 V, 100 (_is) and excellent retention (10-year memory window of 6 V with small charge loss rate; ~l/5 of that of Si3N4). GaN and ZnO trap devices also showed the photo-sensitive programming due to their optoelectronics properties, providing the possibility of developing new type of high performance image sensor (QE ~ 80%)

Tob is a potential marker gene for the basal layer of the epidermis and is stably expressed in human primary keratinocytes

Background  Epidermis consists of multiple layers, from the proliferating basal layer to terminal differentiated cornified layers, and these layers are defined by differentiation status. Tob gene product is known to be a member of the BTG antiproliferative protein family. We investigated the expression pattern of Tob gene product to understand the possible role in differentiation of keratinocytes and epidermis.

Improvement of crosstalk on 5M CMOS image sensor with 1.7x1.7μm2 pixels

Crosstalk of CMOS Image Sensor (CIS) causes degradation of spatial resolution, color mixing and leads to image noise. Crosstalk consists of spectral, optical and electrical components, but definition of each component is obscure and difficult to quantify. For the first time, quantifiable definition of each component is proposed to perform crosstalk analysis in this paper. Contribution of each component to the total crosstalk is analyzed using opto-electrical simulation. Simulation is performed with an internally developed 2D finite difference time domain (FDTD) simulator coupled to a commercial device simulator. Simulation domain consists of set of four pixels. Plane wave propagation from micro-lens to the photodiode is analyzed with FDTD and the optical simulation result is transformed into the photo-current in the photodiode using electrical simulation. The total crosstalk consists of 43% of spectral crosstalk, 14% of optical cross talk, and 43% of electrical crosstalk at the normal incident light. Spectral crosstalk can be suppressed through careful selection of color filter materials with good selectivity of color spectrum. Characteristics of crosstalk and photosensitivity show contrary trend to one another as a function of color filter thickness. Therefore, the crosstalk target is fixed and simulation is performed to determine the minimum color filter thickness that satisfies the crosstalk target. By color filter material and thickness optimization, 10% increase in photosensitivity and 7% decrease spectral crosstalk were obtained. Electrical crosstalk showed 11% and 9% improvement through applying to new implantation process and stacking multi-epi layer on the p-type substrate, respectively.

Factors affecting quality of life in patients with vitiligo: a nationwide study

Little is known about factors affecting the quality of life (QoL) of patients with vitiligo, and previous studies have shown conflicting results.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

7.1 A 1/4-inch 8Mpixel CMOS image sensor with 3D backside-illuminated 1.12μm pixel with front-side deep-trench isolation and vertical transfer gate

According to the trend towards high-resolution CMOS image sensors, pixel sizes are continuously shrinking, towards and below 1.0μm, and sizes are now reaching a technological limit to meet required SNR performance [1-2]. SNR at low-light conditions, which is a key performance metric, is determined by the sensitivity and crosstalk in pixels. To improve sensitivity, pixel technology has migrated from frontside illumination (FSI) to backside illumiation (BSI) as pixel size shrinks down. In BSI technology, it is very difficult to further increase the sensitivity in a pixel of near-1.0μm size because there are no structural obstacles for incident light from micro-lens to photodiode. Therefore the only way to improve low-light SNR is to reduce crosstalk, which makes the non-diagonal elements of the color-correction matrix (CCM) close to zero and thus reduces color noise [3]. The best way to improve crosstalk is to introduce a complete physical isolation between neighboring pixels, e.g., using deep-trench isolation (DTI). So far, a few attempts using DTI have been made to suppress silicon crosstalk. A backside DTI in as small as 1.12μm-pixel, which is formed in the BSI process, is reported in [4], but it is just an intermediate step in the DTI-related technology because it cannot completely prevent silicon crosstalk, especially for long wavelengths of light. On the other hand, front-side DTIs for FSI pixels [5] and BSI pixels [6] are reported. In [5], however, DTI is present not only along the periphery of each pixel, but also invades into the pixel so that it is inefficient in terms of gathering incident light and providing sufficient amount of photodiode area. In [6], the pixel size is as large as 2.0μm and it is hard to scale down with this technology for near 1.0μm pitch because DTI width imposes a critical limit on the sufficient amount of photodiode area for full-well capacity. Thus, a new technological advance is necessary to realize the ideal front DTI in a small size pixel near 1.0μm.