Chang-Rok Moon

Application of Plasma-Doping (PLAD) Technique to Reduce Dark Current of CMOS Image Sensors

Plasma doping (PLAD) was applied to reduce the dark current of CMOS image sensor (CIS), for the first time. PLAD was employed around shallow trench isolation (STI) to screen the defective sidewalls and edges of STI from the depletion region of photodiode. This technique can provide not only shallow but also conformal doping around the STI, making it a suitable doping technique for pinning purposes for CISs with sub-2-mum pixel pitch. The measured results show that temporal noise and dark signal deviation as well as dark level decrease

Novel Charge Trap Devices with NCBO Trap Layers for NVM or Image Sensor

ZnO or AlxGa1-xN charge trap device showed large memory window (>7V) with fast P/E speed (plusmn17 V, 100 (_is) and excellent retention (10-year memory window of 6 V with small charge loss rate; ~l/5 of that of Si3N4). GaN and ZnO trap devices also showed the photo-sensitive programming due to their optoelectronics properties, providing the possibility of developing new type of high performance image sensor (QE ~ 80%)

Deep Trench Isolation for Crosstalk Suppression in Active Pixel Sensors with 1.7 µm Pixel Pitch

A deep trench isolation (DTI) process with a 4 µm deep trench has been developed and successfully applied to 5-megapixel complementary metal oxide silicon (CMOS) image sensors with a 1.7 µm pixel pitch. It was found that from the results of simulations and experiments, DTI is very effective for reducing electrical crosstalk without degrading other pixel characteristics, such as full well capacity, sensitivity, and white spot density. Therefore, DTI could be a solution for obtaining a high performance for CMOS image sensors with a small pixel size of sub-2.0 µm.

Improvement of crosstalk on 5M CMOS image sensor with 1.7x1.7μm2 pixels

Crosstalk of CMOS Image Sensor (CIS) causes degradation of spatial resolution, color mixing and leads to image noise. Crosstalk consists of spectral, optical and electrical components, but definition of each component is obscure and difficult to quantify. For the first time, quantifiable definition of each component is proposed to perform crosstalk analysis in this paper. Contribution of each component to the total crosstalk is analyzed using opto-electrical simulation. Simulation is performed with an internally developed 2D finite difference time domain (FDTD) simulator coupled to a commercial device simulator. Simulation domain consists of set of four pixels. Plane wave propagation from micro-lens to the photodiode is analyzed with FDTD and the optical simulation result is transformed into the photo-current in the photodiode using electrical simulation. The total crosstalk consists of 43% of spectral crosstalk, 14% of optical cross talk, and 43% of electrical crosstalk at the normal incident light. Spectral crosstalk can be suppressed through careful selection of color filter materials with good selectivity of color spectrum. Characteristics of crosstalk and photosensitivity show contrary trend to one another as a function of color filter thickness. Therefore, the crosstalk target is fixed and simulation is performed to determine the minimum color filter thickness that satisfies the crosstalk target. By color filter material and thickness optimization, 10% increase in photosensitivity and 7% decrease spectral crosstalk were obtained. Electrical crosstalk showed 11% and 9% improvement through applying to new implantation process and stacking multi-epi layer on the p-type substrate, respectively.

The Features and Characteristics of 5-mega CMOS Image Sensor with Topologically Unique 1.7/spl m/m~1.7/spl mu/m Pixels

CMOS image sensor (CIS) of 5-mega pixel density has been successfully developed with the smallest pixels (1.7mumtimes1.7mum) ever made. The newly introduced unique pixel architecture brought excellent optical symmetry and high electron capacity. Degradation of sensitivity and cross-talk can be suppressed with the optimization of the optical structure through proper color filter material and reduction of total aspect ratio (vertical stack height/pixel pitch) with Cu back end of line (BEOL)

A 1/2.33-inch 14.6M 1.4μm-pixel backside-illuminated CMOS image sensor with floating diffusion boosting

As pixel sizes continue to scale down, backside-illuminated (BSI) technology has been recently adopted as a solution to improve pixel SNR performance [1,2]. In addition, as the application of image sensors widens from digital still cameras to digital camcorders, high-resolution and high-speed operation are required. This paper presents 1/2.33-inch 14.6Mpixel CMOS image sensor employing a 1.4μm BSI pixel architecture with a floating-diffusion (FD) boosting scheme that enables high SNR and high speed read-out.

Dedicated process architecture and the characteristics of 1.4 μm pixel CMOS image sensor with 8M density

A 1.4 μm-pitch pixel of CMOS image sensor, which is the smallest to date, has been successfully developed and integrated into 8M density for the first time. To overcome the crucial degradation of the saturation charge and sensitivity, a novel photodiode structure extended under transfer gate and an elaborate optical design including very thin tungsten pixel routing with 65 nm-grade design rules are introduced, which result in enhanced electrical and optical performance.

Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications

7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. AVT of 6T HD SRAM cell are 1.29 for PD (PG) and 1.34 for PU, respectively.

1/2.5" 8 mega-pixel CMOS Image Sensor with enhanced image quality for DSC application

Technology and characteristics of 8-mega density CMOS image sensor (CIS) with unit pixel size of 1.75times1.75mum2 are introduced. With recessed transfer gate (RTG) structure and other sophisticated process/device technology, remarkably enhanced saturation capacity and ultra-low dark current have been obtained, which satisfy the requirements of high density digital still camera (DSC) application

The features and characteristics of 5M CMOS image sensor with 1.9/spl times/1.9/spl mu/m/sup 2/ pixels

5 mega CMOS image sensor with 1.9mum-pitch pixels has been implemented with 0.13 mum low power CMOS process. By applying 4-shared pixel architecture, 2.5V operation voltage, and tight design rules for some critical layers in pixels, high fill factor and the corresponding high saturation could be obtained. Image lag was sufficiently suppressed by pulse-boosting of transfer gate voltage and electrical cross-talk was suppressed by use of n-type epitaxial layer. It is shown that several sophisticated processes improve sensitivity, temporal random noise, and dark current. With this technology, full 5-mega density CMOS image sensor chips have been successfully developed