Sang Yeol Lee

High-Performance a-IGZO TFT With

We have investigated the high-performance oxide thin-film transistor (TFT) with an amorphous indium gallium zinc oxide (a-IGZO) channel and ZrO2 gate dielectrics. The a-IGZO TFT is fully fabricated at room temperature without any thermal treatments. ZrO2 is one of the most promising high-k materials. The a-IGZO TFT (channel W/L = 240/30 ¿m) with ZrO2 shows high performance such as high on current of 2.11 mA and high field effect mobility of 28 cm2/(V·s) at the gate voltage 10 V. The threshold voltage and the subthreshold swing are 3.2 V and 0.56 V/decade, respectively. Note that the high-performance a-IGZO TFT is higher than ever shown in previous researches.

\hbox{ZrO}_{2}

Time dependence of the threshold voltage (Vth) shift in amorphous hafnium-indium-zinc oxide (a-HIZO) thin film transistor has been reported under on-current bias temperature stress measured at 60 °C. X-ray photoelectron spectroscopy results show the decrease in oxygen vacancies by Hf metal cations in a-HIZO systems after annealing process. High stability of a-HIZO systems has been observed due to low charge injection from the channel layer. Hf metal cations have been effectively incorporated into the IZO thin films as a suppressor against both the oxygen deficiencies and the carrier generation.

Gate Dielectric Fabricated at Room Temperature

Amorphous silicon–indium–zinc–oxide (a-SIZO) thin film transistor (TFT) was investigated with the process temperature below 150 °C. The a-SIZO TFT exhibited a field effect mobility of 21.6 cm2/V s and an on/off ratio of 107. The stabilities of a-SIZO TFT and indium–zinc–oxide (IZO) TFT were compared, and a-SIZO TFT showed 3.7 V shift for threshold voltage (Vth) compared to 10.8 V shift in IZO TFT after bias temperature stress. Si incorporation into IZO-system as a stabilizer, which was confirmed by x-ray photoelectron spectroscopy, resulted in small shift in Vth in a-SIZO TFT without deteriorating mobility of higher than 21.6 cm2/V s.

High stability of amorphous hafnium-indium-zinc-oxide thin film transistor

Charge trapping is dramatically suppressed in ZnO transparent thin film transistors (TFTs) employing a multilayered gate insulator with HfO2 layer sandwiched by Al2O3 layers. In spite of its high dielectric constant, HfO2 has critical drawbacks including huge charge trap density in interfaces. We suggest and demonstrate an elegant solution to minimize the charge trapping introducing Al2O3 buffer layers. The operation of Al2O3∕HfO2∕Al2O3 multilayered gate-insulator structure in the ZnO transparent TFT is evaluated to ensure the voltage difference in the hysteresis loop as low as 0.2V, and the immunization to the threshold voltage shift induced by repeated sweeps of gate voltage.

Amorphous silicon–indium–zinc oxide semiconductor thin film transistors processed below 150 °C

We report on the origin of threshold voltage shift with the thickness of amorphous InGaZnO channel layer deposited by rf magnetron sputter at room temperature, using density of states extracted from multi frequency method and falling rates of activation energy, which of trends are entirely consistent each other in respect of the reduction of total traps with increasing the channel thickness. Furthermore, we shows that the behavior of ΔVth under the positive gate bias stress and thermal stress can be explained by charge trapping mechanism based on total trap variation.

Efficient suppression of charge trapping in ZnO-based transparent thin film transistors with novel Al2O3/HfO2/Al2O3 structure

High-performance thin-film transistors (TFTs) are the fundamental building blocks in realizing the potential applications of the next-generation displays. Atomically controlled superlattice structures are expected to induce advanced electric and optical performance due to two-dimensional electron gas system, resulting in high-electron mobility transistors. Here, we have utilized a semiconductor/insulator superlattice channel structure comprising of ZnO/Al2O3 layers to realize high-performance TFTs. The TFT with ZnO (5 nm)/Al2O3 (3.6 nm) superlattice channel structure exhibited high field effect mobility of 27.8 cm2/Vs, and threshold voltage shift of only < 0.5 V under positive/negative gate bias stress test during 2 hours. These properties showed extremely improved TFT performance, compared to ZnO TFTs. The enhanced field effect mobility and stability obtained for the superlattice TFT devices were explained on the basis of layer-by-layer growth mode, improved crystalline nature of the channel layers, and passivation effect of Al2O3 layers.

Effect of channel thickness on density of states in amorphous InGaZnO thin film transistor

The feasibility of controlling the threshold voltage (Vth) and field effect mobility (μFE) has been studied by adjusting hafnium ratio. Hafnium zinc tin oxide (HZTO) thin films were fabricated with various hafnium ratios. Vth shifted toward positive direction, and the μFE was decreased due to the decrease of carrier concentration, because hafnium acts as carrier suppressor. The subthreshold swing exhibits good properties from 1.01 to 0.44. The decrease of carrier concentration in HZTO is closely related with the decrease of the number of oxygen by hafnium ion.

Artificial semiconductor/insulator superlattice channel structure for high-performance oxide thin-film transistors

Silicon effect on the performance of amorphous silicon-indium-zinc-oxide (a-SIZO) films has been investigated for thin-film transistor applications depending on composition ratio and annealing-temperature. X-ray diffraction, x-ray photoelectron spectroscopy, and time-of-flight secondary-ion-mass-spectrometry have been used to characterize the properties of SIZO thin-film channel layer with different Si concentrations and annealing-temperatures. Those results revealed that Si is more strongly binding with oxygen since their high metal-oxygen bonding-strength and low standard electric potential, which result in implying Si, allow the amorphous oxide semiconductors to achieve oxide-lattice structures even at a low-temperature of 150 °C.

Effect of hafnium addition on Zn-Sn-O thin film transistors fabricated by solution process

The effect of Hf addition on the electrical performance and bias stability of ZnO-based thin-film transistors (TFTs) has been investigated. All channel layers were deposited by atomic layer deposition with various Hf contents. In addition, multilayer oxide channel TFTs consisting of two or three Hf-doped ZnO (HZO) and ZnO layers were developed for the realization of adequate channel mobility and electrical stability. The subthreshold swing and bias stability were improved by the deposition of the thin-HZO layers with amorphous phase as the first and final channel layers. The use of a conductive ZnO layer enhanced the device mobility. The oxide TFTs with a multilayer channel of a-HZO/ZnO/ a-HZO exhibited relatively good stability and mobility due to the reduced interface trap density between the channel and dielectric layers, and the suppressed adsorption of negatively charged oxygen on the back channel. The origin of the stability issues and novel channel design are proposed on the basis of the electrical performance of various TFT structures.

Role of silicon in silicon-indium-zinc-oxide thin-film transistor

Effect of trap-density of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were studied using different analysis of x-ray photoelectron spectroscopy (XPS) depth profile and density of states (DOSs). To change trap-densities systematically, rf-power was varied to cause different effect on the initial growth stage of a-IGZO layer grown on gate insulator. The interfacial trap-density was confirmed to be dominant effect on the performance and the threshold voltage shift of a-IGZO TFT by observing the variation of O1s binding energy from XPS. The relation between temperature stress induced and trap-density in deep level was investigated by analyzing DOSs.