Yoon-Soo Chun

A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs

In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.

Highly manufacturable 4 Gb DRAM using using 0.11 /spl mu/m DRAM technology

4 Gb DRAM has been developed successfully using 0.11 /spl mu/m DRAM technology. Considering manufacturability, we have focused on developing patterning technology that makes 0.11 /spl mu/m design rules possible using KrF lithography. Also, novel DRAM technologies, which have a big influence on the future DRAM integration, are developed as follows:, using novel oxide (SOG) for the enhanced capability of gap-filling, borderless metal contact and stud processes, line-type storage node SAC, thin gate oxide, and CVD Al process for metal interconnections.

Highly manufacturable 90 nm DRAM technology

A 90 nm DRAM technology has been successfully developed using 512 Mb DRAM for the first time. ArF lithography is used for printing critical layers with resolution enhancement techniques. A novel gap-filling technology using spin coating oxide is developed for STI and ILD processes. A diamond-shaped storage node is newly developed for large capacitor area with better mechanical stability. A CVD Al process can make the back-end metallization process simple and easy. A dual gate oxide scheme can provide independent optimization for memory cell transistor and periphery support device so that the off-state leakage current of the cell transistor can be maintained below 0.1 fA.

A 1T/1C Ferrodectric RAM Using A Double-level Metal Process For Highly Scalable Nonvolatile Memory

A double-level metal, one-poly, 1T/lC 64k ferroelectric RAM has been successfully fabricated with 1.2~ conventional CMOS technology. By realizing aluminum bit line, aluminum plate line in the doublelevel metal process without degrading Pt/PZT/Pt ferroelectric capacitor and by adopting lT/lC cell archtecture, lOOns data access time was obtained at Vcc=S.OV which is faster by 40% than the commercialized 2T/2C FRAM with a single-level metal. A proper annealing processes was proved to be the key for the recovery of the ferroelectric capacitor degradation caused by the double-level metal integration process.

A highly reliable 1T/1C ferroelectric memory

A reliable 1T/1C ferroelectric RAM has been successfully fabricated with 1.2 /spl mu/m conventional CMOS technology by adopting IrO/sub 2/ electrode and the Ti-rich PZT thin film. The Ti-rich PZT capacitor shows no degradation of sensing Pr after integration process. After 1/spl times/10/sup 10/ cycling, the loss of remnant polarization was less than 5%. In thermally accelerated (150/spl deg/C) test condition, more than 14 /spl mu/C/cm/sup 2/ for both data 0 and data 1 sensing Pr values are obtained even after 10 years.

Highly manufacturable and high performance SDR/DDR 4 Gb DRAM

A 4 Gb SDR/DDR DRAM is fabricated with 0.11 /spl mu/m CMOS technology. To the best of our knowledge, this is the first working DRAM ever achieved at such a high density. The cell size and chip size of the 4 Gb DRAM are approximately 0.1 /spl mu/m/sup 2/ and 645 mm/sup 2/, respectively. The key technologies developed for this 4 Gb DRAM are KrF lithography with RET, novel ILD gap-filling, full SAC with LSC, novel W-BL, low-temperature Al/sub 2/O/sub 3/ MIS capacitor, and triple level CVD-Al interconnection technology. The key features of these technologies were reported elsewhere (Jeong et al., Tech. Digest of IEDM, pp. 353-6, 2000). The summary of 0.11 /spl mu/m DRAM technology is listed and compared with our previous 0.13 /spl mu/m (Kim et al., 2000) and 0.15 /spl mu/m (Kim et al., 1998) generations. We have found that random single-bit and/or twin-bit failures and block failures are the most critical issues to be solved for achieving good functionality of 4 Gb DRAM. In order to get rid of the single and twin bit failures, 80 nm array transistors, sub-80 nm memory cell contacts and mechanically robust capacitors are developed and triple-level CVD Al technology is optimized to reduce block failure as well as improve chip performance. In this paper, these technologies for achieving good functionality with high performance are highlighted in detail.

A DRAM technology using MIM BST capacitor for 0.15 /spl mu/m DRAM generation and beyond

Recently, 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) and 0.15 /spl mu/m technology node for 4 Gb DRAM have been successfully demonstrated. These two technology generations are based on MIS capacitors using Ta/sub 2/O/sub 5/ dielectric. The extension of Ta/sub 2/O/sub 5/ MIS capacitors below 0.15 /spl mu/m technology is considered to be difficult due to insufficient cell capacitance. It is widely accepted that the MIM capacitor using high dielectric constant material is inevitable for 0.15 /spl mu/m technology and beyond. Although many studies to use high dielectric material have been reported, those studies are not adequate for 0.15 /spl mu/m technology and beyond because most of the studies are either based on a simple capacitor module process or based on large feature size design rules. In this paper, for the first time, a DRAM technology using BaSrTiO/sub 3/ (BST) MIM capacitors is developed with 0.15 /spl mu/m technology.

A new DRAM cell technology using merged process with storage node and memory cell contact for 4 Gb DRAM and beyond

A new DRAM cell scheme using merged process with storage node and memory cell contact called BC is introduced for free alignment tolerance between memory cell contact and storage node. The new cell scheme and conventional COB stacked cell scheme are compared for the misalignment tolerance and photo and etch process issues. The new cell scheme is processed in 0.15 /spl mu/m minimum feature size and its results are described including vertical SEM pictures, capacitance-voltage data, and leakage current. This new cell scheme achieved the requirement of memory cell capacitance of 25 fF/cell in 0.30 /spl mu/m pitched 4 Gb DRAMs.

A novel cell-STP (storage node through plate node) cell-technology for multigigabit-scale DRAM and logic-embedded DRAM generations

A novel cell technology has been developed to overcome process issues related with successful downscaling of a DRAM memory cell and to produce a reliable and manufacturable cell. Storage node in the proposed cell is formed in a self-aligned manner through the plate node after the formation of plate node and capacitor dielectric. Considering the scalability of the novel cell and experimental results showing the charge storage capacitance of 25fF/cell, leakage current less than 1fA/cell, and excellent time-to-dielectric breakdown characteristics, it is expected that this novel cell technology can be a promising candidate for the 1Gb DRAM and beyond as well as logic-embedded DRAM.