Sanghyuk Jung

FRA: a flash-aware redundancy array of flash storage devices

Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as storage media in the embedded and computer system environments. In the case of reliability, however, there are many shortcomings in flash memory: potentially high I/O latency due to erase-before-write and poor durability due to limited erase cycles. To overcome these problems, a RAID technique borrowed from storage technology based on hard disks is employed. In the RAID technology, multi-bit burst failures in the page, block or device are easily detected and corrected so that the reliability can be significantly enhanced. However the existing RAID-5 scheme for the flash-based storage has delayed response time for parity updating. To overcome this problem, we propose a novel approach using a RAID technique in flash storage, called Flash-aware Redundancy Array. In this approach, parity updates are postponed so that they are not included in the critical path of read and write operations. Instead, they are scheduled for when the device becomes idle. For example, the proposed scheme shows a 19% improvement in the average write response time, compared to other approaches.

A process-aware hot/cold identification scheme for flash memory storage systems

NAND flash memory has attractive features compared to hard disk drives such as small size, no mechanical noise and shock resistance. But it also has some drawbacks such as no support for in-place updates and limited program/erase cycles, which trigger the development of sophisticated buffer management algorithms in order to reduce write and/or erase operations to flash memory. The significant gap in update frequency between hot and cold data motivates us to separate hot and cold data on different flash blocks to avoid unnecessary program/erase cycles. Many buffer management algorithms determine a request to be hot or cold based on its requested data size. However, the data size could become a wrong indicator of update frequency in many applications. In this paper, we propose a new hot/cold identification scheme in order to increase identification accuracy and, thus, to enhance storage performance and durability by reducing program/erase cycles. The proposed technique uses the process identification used in many operating systems as a hot/cold indicator. The experimental results show that the proposed scheme contributes to high performance and durability as compared to previously proposed identification schemes.

Hierarchical architecture of flash-based storage systems for high performance and durability

The use of NAND flash memory for building permanent storage has been increasing in many embedded systems due to properties such as non-volatility and low enery consumption. The persistent requirements for high storage capacity have given rise to the increase of bit density per cell as in multi-level cells but this has come at the expense of performance and has resulted in degradation of durability. In this paper, we introduce a complementary approach to boost the performance and durability of MLC-based storage systems by employing a non-volatile buffer that temporarily holds the data heading to MLCs. We also propose algorithms to efficiently eliminate unnecessary write and erase operations in MLCs by performing a pre-merge in the buffer. Our experiments show that the proposed approach can increase performance by up to 4 times and durability by 4 times by adding only a small hardware cost.

Write-aware buffer management policy for performance and durability enhancement in NAND flash memory

The popularity of NAND flash memory has been growing rapidly in recent years, but the SSD (Solid-State Disk) has shown limited success in its battle against the hard disk. Besides the high price, SSD suffers performance degradation under random write requests, due to the intrinsic weak points of NAND flash: erase-before-write, asymmetric read/write access time, and limited program/erase cycles. In order to overcome these drawbacks, many buffer replacement algorithms have been proposed. However, considering the cost of write operations, it would be beneficial to have dirty pages updated before being flushed to flash memory. In this paper, we propose a new buffer management scheme to retain write-intensive pages in the buffer, and we confirm its effectiveness by applying it to one of the existing buffer management schemes. The simulation results indicate that the proposed scheme reduces up to 30% of the write count, and, therefore, extends the lifetime of NAND flash memories.

Architecture exploration of flash memory storage controller through a cycle accurate profiling

Recently, NAND flash memory has been widely adopted as a storage medium in various devices such as mobile phones, MP3 players, and digital cameras. In particular, Solid State Drives (SSDs), which are composed of multiple NAND flash memories, have gradually replaced hard disk drives (HDD). However, SSDs have an inherent weakness stemming from NAND flash memory and its complex architecture. This phenomenon makes it difficult to analyze and optimize the performance of SSD controllers. To overcome this weakness, highly accurate system simulations are needed for exploring architectural parameters to maximize the performance during the design phase. In this paper, we implement a simulator that considers all of the hardware components in SSD to assist in generating quantitatively accurate analysis when an algorithm or controller is realized. This simulator models the detailed characteristics of hardware components such as operation clock frequency and resource conflicts in order to represent SSD in great detail. In the experiments section, we verify the impacts of interface speed, page size, and other configuration parameters by using this cycle accurate simulator. These analysis results can then be used as raw data for optimization.

Hierarchical use of heterogeneous flash memories for high performance and durability

The use of NAND flash memory for building permanent storage has been increasing in many embedded systems due to idiosyncrasies such as non-volatility and low energy consumption. The persistent requirements for high storage capacity have given rise to the increase of bit density per cell as in multi-level cells but this has come at the expense of performance and has resulted in degradation of durability. In this paper, we introduce a complementary approach to boost the performance and durability of MLC-based storage systems by employing a non-volatile buffer that temporarily holds the data heading to MLCs. We also propose algorithms to efficiently eliminate unnecessary write and erase operations in MLCs by performing a pre-merge in the buffer. Our experiments show that the proposed approach can decrease average response time by up to 4 times and increase durability by 4 times by adding only a small hardware cost.

LINK-GC: a preemptive approach for garbage collection in NAND flash storages

In NAND flash storages, the invalidated pages could occupy the storage space until being erased. In order to preserve sustained write performance and storage capacity, the storage controller must eliminate these pages through garbage collection operations. However, the garbage collection operations may cause high computation overhead while selecting victim blocks, thereby resulting in the host system suffering from unendurable storage-access latency as well as performance degradation. In this paper, we propose an efficient garbage collection mechanism, which not only eliminates the computation overhead in victim block selection, but also improves responsiveness to the host requests by making the garbage collection operation preemptive.

Data loss recovery for power failure in flash memory storage systems

Abstract Due to the rapid development of flash memory technology, NAND flash has been widely used as a storage device in portable embedded systems, personal computers, and enterprise systems. However, flash memory is prone to performance degradation due to the long latency in flash program operations and flash erasure operations. One common technique for hiding long program latency is to use a temporal buffer to hold write data. Although DRAM is often used to implement the buffer because of its high performance and low bit cost, it is volatile; thus, that the data may be lost on power failure in the storage system. As a solution to this issue, recent operating systems frequently issue flush commands to force storage devices to permanently move data from the buffer into the non-volatile area. However, the excessive use of flush commands may worsen the write performance of the storage systems. In this paper, we propose two data loss recovery techniques that require fewer write operations to flash memory. These techniques remove unnecessary flash writes by storing storage metadata along with user data simultaneously by utilizing the spare area associated with each data page.

In-page management of error correction code for MLC flash storages

Memory manufacturers have recently advanced silicon technology to implement the multi-level cell technique onto NAND flash for the reduction of per-bit device cost. However, this technical improvement has introduced an additional problem of reliability and/or durability degradation, leading to the inevitable use of error detection and correction techniques. To increase the number of correctable error bit in recent flash memories, ECC techniques tend to use longer code bits. As the silicon technology of NAND device evolves, such growing code bits for a user data page could overflow its corresponding spare area in later devices. In this paper, we propose a novel management mechanism of excessively long error correction codes using user data area. The proposed mechanism is capable of providing error correction capability for highly error-prone NAND devices by efficiently managing long ECC codes only with negligible performance degradation.

Compression ratio based hot/cold data identification for flash memory

This paper presents a hot/cold data identification technique for NAND flash storage systems. The proposed technique uses both compression ratio and sector size of requested data as identification criteria. In order to avoid high overhead due to compression process, the technique determines compression ratio using a fraction of data. The experimental results show that this technique contributes to effectively identify hot data and when used in buffer management to increase the hit rate effectively.