Yang-Sup Lee

FRA: a flash-aware redundancy array of flash storage devices

Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as storage media in the embedded and computer system environments. In the case of reliability, however, there are many shortcomings in flash memory: potentially high I/O latency due to erase-before-write and poor durability due to limited erase cycles. To overcome these problems, a RAID technique borrowed from storage technology based on hard disks is employed. In the RAID technology, multi-bit burst failures in the page, block or device are easily detected and corrected so that the reliability can be significantly enhanced. However the existing RAID-5 scheme for the flash-based storage has delayed response time for parity updating. To overcome this problem, we propose a novel approach using a RAID technique in flash storage, called Flash-aware Redundancy Array. In this approach, parity updates are postponed so that they are not included in the critical path of read and write operations. Instead, they are scheduled for when the device becomes idle. For example, the proposed scheme shows a 19% improvement in the average write response time, compared to other approaches.

A process-aware hot/cold identification scheme for flash memory storage systems

NAND flash memory has attractive features compared to hard disk drives such as small size, no mechanical noise and shock resistance. But it also has some drawbacks such as no support for in-place updates and limited program/erase cycles, which trigger the development of sophisticated buffer management algorithms in order to reduce write and/or erase operations to flash memory. The significant gap in update frequency between hot and cold data motivates us to separate hot and cold data on different flash blocks to avoid unnecessary program/erase cycles. Many buffer management algorithms determine a request to be hot or cold based on its requested data size. However, the data size could become a wrong indicator of update frequency in many applications. In this paper, we propose a new hot/cold identification scheme in order to increase identification accuracy and, thus, to enhance storage performance and durability by reducing program/erase cycles. The proposed technique uses the process identification used in many operating systems as a hot/cold indicator. The experimental results show that the proposed scheme contributes to high performance and durability as compared to previously proposed identification schemes.

A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based Applications

In this paper, we propose a novel FTL (flash translation layer) architecture for NAND flash based applications such as mp3 players, DSCs (Digital still camera) and SSDs (Solid-state disk). Even though the basic function of an FTL is to translate a logical sector address to a physical sector address in flash memory, its efficient algorithms have a significant impact on performance as well as lifetime. After we categorize dominant parameters that affect performance and endurance, we explore the design space of the FTL architecture based on a diverse workload analysis. With our FTL architectural framework, we can decide which configuration of FTL mapping parameters yields the best performance depending on each NAND flash application behavior.

An efficient management scheme for updating redundant information in flash-based storage system

Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as a storage media in embedded and computer system environments. However, there are many shortcomings in flash memory such as potentially high I/O latency due to erase-before-write and poor durability due to limited erase cycles. To address these performance and reliability anomalies, many large-scale storage systems use redundancy-based parallel access schemes such as RAID techniques. However, such redundancy-based schemes incur high overhead due to generating and storing redundancy information, especially in flash-based storage systems. In this paper, we propose a novel and performance-effective approach using a redundancy-based data management scheme in flash storage, called Flash-aware Redundancy Array. The proposed technique not only reduces the redundancy management overhead by performing redundancy update operations during idle periods, but also provides a preventive mechanism to recover data from unexpected read errors occurring before such redundancy update operations finish. From the experiments, we found that the proposed technique improves flash-based storage systems by 19% in average execution time as compared to other redundancy-based approaches.