Sangjoo Lee

Development of a Production-Ready, Back-Illuminated CMOS Image Sensor with Small Pixels

A back-illuminated 2 megapixel CMOS sensor utilizing mature wafer manufacturing operations is described. Sensitivity, dark current and other key pixel performance measures are compared against an equivalent conventional sensor. Aspects of the process integration that make the technology manufacturable are described. Simulations that predict the performance of a full color sensor are discussed.

Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 µA/µm and 756 µA/µm respectively at 0.9 V and 1 nA/µm Ioff with the novel high-k/metal (HKMG) gate stack and advanced strain engineering. Short channel effect is successfully suppressed thanks to the optimized shallow junction, resulting in excellent DIBL and subthreshold swing below 120 mV and 90 mV/dec, respectively. In addition, full functionality of SRAM device with 20 nm technology architecture is confirmed.

50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications

A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.

The effects of TaN thickness and strained substrate on the performance and PBTI characteristics of poly-Si/TaN/HfSiON MOSFETs

The effects of TaN metal-gate thickness on the electrical characteristics of poly-Si/metal-gate/HfSiON MOSFETs have been investigated. Too thin TaN was reactive with poly-Si gate, which led to the formation of Si-doped metal gate. As a result, the work function of the metal gate was reduced and the capacitance increased while generating traps in HfSiON films. P-MOSFET using poly-Si/TaN gate with channel engineering in strained-Si substrate showed threshold voltage of - 0.45 V at W/L= 10/1 /spl mu/m and improved MOSFET characteristics.

A 1/2.33-inch 14.6M 1.4μm-pixel backside-illuminated CMOS image sensor with floating diffusion boosting

As pixel sizes continue to scale down, backside-illuminated (BSI) technology has been recently adopted as a solution to improve pixel SNR performance [1,2]. In addition, as the application of image sensors widens from digital still cameras to digital camcorders, high-resolution and high-speed operation are required. This paper presents 1/2.33-inch 14.6Mpixel CMOS image sensor employing a 1.4μm BSI pixel architecture with a floating-diffusion (FD) boosting scheme that enables high SNR and high speed read-out.