Hee Sung Kang

Novel body tied FinFET cell array transistor DRAM with negative word line operation for sub 60nm technology and beyond

In this paper, a highly manufacturable 512M FinFET DRAM with novel body tied FinFET cell array transistor on bulk Si substrate has been successfully integrated and the characteristics were compared with RCAT (Recess Channel Array Transistor) and planar cell array transistor DRAM for the first time. We also propose the NWL (Negative Word Line) scheme with low channel doping body tied FinFET for a highly manufacturable FinFET DRAM for sub 60nm technology node.

A novel SiGe-inserted SOI structure for high performance PDSOI CMOSFETs

A novel partially-depleted silicon-on-insulator (PDSOI) CMOSFETs with SiGe-inserted layer have been proposed. The SiGe-inserted layer in NMOS successively suppresses the floating body effects (FBE) by lowering the body-to-source potential barrier to hole current. It also provides a good current performance in PMOS by inducing the change of channel dopant distribution and increasing the efficiency of pocket ion implantation. Consequently, SiGe-inserted SOI devices achieve higher drain-to-source breakdown voltage in NMOS due to the suppression of FBE and increase drive currents of both NMOS and PMOS by 10% and 15%, respectively, compared to conventional PDSOI devices.

Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)

The operational six-transistor SRAM cell was experimentally demonstrated using bulk FinFET CMOS technology. A cell size of 0.79 /spl mu/m/sup 2/ was achieved by 90 nm node technology, with stable operation at 1.2 V using 4 levels of W and Al interconnects. Static noise margin of 280 mV was obtained at V/sub cc/ of 1.2 V. To our knowledge, this represents the first experimental demonstration of a fully integrated bulk FinFET SRAM cell.

Manufacturable embedded CMOS 6T-SRAM technology with high-k gate dielectric device for system-on-chip applications

Manufacturable embedded CMOS 6T-SRAM with the HfO/sub 2/-Al/sub 2/O/sub 3/ dielectric for system-on-chip (SoC) applications is successfully demonstrated for the first time in the semiconductor industry. The possibility of the high-k gate dielectric in low power SoC applications is suggested. 0.11/spl mu/m NFET and PFET devices with thin high-k gate dielectric have 470 and 150/spl mu/A//spl mu/m at Ioff=0.1nA/um and Vdd=1.2V, respectively. Inversion thickness of NFET and PFET are 2.4nm and 2.7nm, respectively. Gate leakage current of the high-k is 1000 times lower than that of the oxynitride at the accumulation region. Static noise margin of 2.14/spl mu/m/sup 2/ 6T-SRAM bit cell is about 300mV at Vdd=1.2V. 6T-SRAM chip yield of the high-k is comparable to that of the oxynitride. The post nitridation after high-k film deposition is very important to the yield of the SRAM chips due to the suppression of the PFET boron penetration. Stand-by current of the SRAM chips with the high-k is shown to be a decreases of 60% compared with the oxynitride.

Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 µA/µm and 756 µA/µm respectively at 0.9 V and 1 nA/µm Ioff with the novel high-k/metal (HKMG) gate stack and advanced strain engineering. Short channel effect is successfully suppressed thanks to the optimized shallow junction, resulting in excellent DIBL and subthreshold swing below 120 mV and 90 mV/dec, respectively. In addition, full functionality of SRAM device with 20 nm technology architecture is confirmed.

50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications

A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.

Optimized cell structure for FinFET array Flash memory

In this paper, a highly manufacturable 256 M body tied tri-gate fin array NOR-type Flash memory, with 70 nm fin width, was successfully fabricated and the characteristics were compared with planar cell array transistors. In this experiment, a 1.6 times higher driving current of the fin array flash memory cell transistor is achieved than that of a planar device with the same gate length. We propose an optimized fin structure for flash memory operation and a direction for enhanced current of the fin array flash memory cell transistor with respect to the channel silicon plane, coupling ratio, junction profile and anti-punch through implantation conditions.

Double raised source/drain transistor with 50 nm gate length on 17 nm UTF-SOI for 1.1 /spl mu/m/sup 2/ embedded SRAM technology

Double raised source/drain (DR) ultra thin film (UTF) SOI CMOSFETs were experimented for the first time. Double Si selective epitaxial growth (SEG) process before source/drain extension and deep source/drain implant is greatly recommended for excellent device performance with a reduced series resistance. Fully depleted (FD) SOI devices with 50 nm gate length for embedded SRAM technology were investigated for different SOI film thickness. Transistor performances of 700 /spl mu/A//spl mu/m and 355 /spl mu/A//spl mu/m at 1.0 V operation and Ioff = 90 nA//spl mu/m was obtained for NMOS and PMOS devices, respectively. Drain induced barrier lowering (DIBL) was improved as the SOI film thickness was scaled down to 17 nm from 50 nm. The static noise margin (SNM) for a 1.1 /spl mu/m/sup 2/ SRAM cell was 210 mV and ring oscillator speed was improved by 24% compared to bulk devices.

Highly stable SOI technology to suppress floating body effect for high performance CMOS device

High performance microprocessors with high stabilities are fabricated on Si and SiGe inserted (SGI) SOI wafers. The operation margins of voltages and frequency are characterized. For body floating devices, the operation margins at high Vdd and low frequency are narrow due to the floating body effect (FBE). These operation limits are drastically improved by applying a body contact for only NMOS at the critical circuits sensitive to the FBE. The maximum operation voltage increases from 1.8 V up to 2.5 V. The minimum operation frequency is lowered from 370 MHz to 220 MHz. The functionality of the NMOS body contact SOI microprocessor is comparable to that of the bulk. To maximize the SOI performance gain, body contacted and floating SOI devices should be optimized, and the smaller portion of body contacted devices are conclusive. For body floating SOI devices, the SGI SOI technology is very effective in suppressing SOI FBE and provides stable circuit operation.

Fully Depleted SOI Complementary MOS Device with Raised Source/Drain for 90 nm Embedded Static RAM Technology

Fully depleted silicon-on-insulator (FD SOI) devices with 70 nm gate lengths for embedded static random access memory (SRAM) technology were investigated for different SOI film thickness. Transistor performances of 700 µA/µm and 320 µA/µm were obtained for n-type and p-type metal-oxide semiconductor field effect transistor (NMOSFET and PMOSFET) devices, respectively at 1.0 V operation voltage and Ioff=75 nA/µm. Si selective epitaxial growth (SEG) process was well optimized. Both the single raised (SR) and double raised (DR) source/drain process were studied to reduce parasitic series resistance. For the DR process, both NMOSFET and PMOSFET performance are improved by 9 and 13% respectively, compared to the SR process. Drain induced barrier lowering (DIBL) was improved from 100 mV to 13 mV as the SOI film thickness was scaled down from 50 nm to 17 nm. Due to the self-heating effect, the AC current is 15% higher than the DC current for the case of 40 nm SOI thickness. The static noise margin (SNM) for a 1.1 µm2 6T-SRAM cell was 210 mV and ring oscillator speed was improved by 24% compared to bulk devices.