Prasad Shabadi

Low-power sub-threshold design of secure physical unclonable functions

The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depends on minute uncontrollable process variations, a low supply voltage can benefit PUFs by providing high sensitivity to variations and low power consumption as well. Motivated by this, we explore the feasibility of sub-threshold arbiter PUFs in 45nm CMOS technology. By modeling process variations and interconnect imbalance effects at the post-layout design level, we optimize the PUF supply voltage for the minimum power-delay product and investigate the trade-offs on PUF uniqueness and reliability. Moreover, we demonstrate that such a design optimization does not compromise the security of PUFs regarding modeling attacks and side-channel analysis attacks. Our final 64-stage sub-threshold PUF design only needs 418 gates and consumes 0.047pJ energy per cycle, which is very promising for low-power wireless sensing and security applications.

Design and Validation of Arbiter-Based PUFs for Sub-45-nm Low-Power Security Applications

Harnessing unique physical properties of integrated circuits to enhance hardware security and IP protection has been extensively explored in recent years. Physical unclonable functions (PUFs) can sense inherent manufacturing variations as chip identifications. To enable the integration of PUFs into low-power and security applications, we study the impacts of process technology and supply voltage scaling on arbiter-based PUF circuit design. A Monte Carlo-based statistical analysis has demonstrated that advanced technologies and reduced supply voltage can improve the PUF uniqueness due to increased delay sensitivity. A linear regression approach has been leveraged to generate PUF delay profile by factoring in device, supply voltage and temperature variations. An accurate SVM-based software modeling analysis is used to verify the PUF additive delay behavior. Finally, postsilicon validation on arbiter-based PUF test chips in 45 nm SOICMOS technology has been correlated to simulation results and the inconsistency has been discussed. The test chips can resist the basic support vector machine attack due to the dynamic circuit effects and the limitation of our delay model.

Spin wave functions nanofabric update

We provide a comprehensive progress update on the magnonic spin wave functions nanofabric. Spin wave propagation does not involve any physical movement of charge particles. Information is encoded in the phase of the wave and computation is based on the principle of superposition. This provides a fundamental advantage over conventional charge based electronics and opens new horizons for novel nano-scale architectures. The coupling mechanism between the spin and charge domain is enabled by the Magneto-Electric (ME) cells. Based on our experimental work we show that, an electric field of ∼1MV/m would be required to obtain 90 degree magnetization rotation. The paper also provides a methodology for estimating ME cell switching energy. In particular, we show that this energy can be as low as 10aJ. In addition, we discuss different topology options and circuit styles for 1-bit/2-bit magnonic adders. Our estimates on benefits vs. 45nm CMOS implementation show that, for a 1-bit adder, ∼40X reduction in area and ∼60X reduction in power is possible with the spin wave based implementation. For the 2-bit adder, results show that ∼33x area reduction and ∼40X reductions in power may be possible.

Towards logic functions as the device

This paper argues for alternate state variables and new types of sophisticated devices that implement more functionality in one computational step than typical devices based on simple switches. Elementary excitations in solids enabling wave interactions are possible initial candidates to create such new devices. The paper focuses on magnon-based spin-wave-logic functions (SPWF) and presents high fan-in majority, weighted high fan-in majority, and frequency-multiplexed weighted high fan-in majority devices as initial SPWFs. Experiments proving feasibility are also shown. Benefits vs. scaled CMOS are quantified. Results show that for 128 or larger inputs even a 2.5µm SPWF carry-look-ahead adder implementation is faster than the 45nm CMOS version. The 45nm SPWF adder is expected to be significantly faster across the whole range of input widths. In particular, the 45nm SPWF CLA adder is estimated to be at least 77X faster than CMOS version for input widths equal to or greater than 1024. A second example of a counter circuit is presented to illustrate the considerable reduction in complexity possible vs. CMOS.

DESIGN OF SPIN WAVE FUNCTIONS-BASED LOGIC CIRCUITS

Over the past few years, several novel nanoscale computing concepts have been proposed as potential post-complementary metal oxide semiconductor (CMOS) computing fabrics. In these, key focus is on inventing a faster and lower power alternative to conventional metal oxide semiconductor field effect transators. Instead, we propose a fundamental shift in mindset towards more functional building blocks, replacing simple switches with more sophisticated information encoding and computing based on alternate state variables to achieve a significantly more efficient and compact logic. Specifically, we propose wave computation enabled by magnetic spin wave interactions called as spin wave functions (SPWFs). In SPWFs, computation is based on wave interference and information can be encoded in a waves phase, amplitude and frequency. In this paper, we provide an update on key fabric concepts and design aspects. Our analysis shows that circuit design choices can have a significant impact on overall fabric/device capabilities required and vice versa. Thereby, we adapt an integrated fabric-circuit exploration methodology. Control schemes for wave streaming and synchronization are also discussed with several SPWF circuit topologies. Our estimations show that significant area and power benefits can be expected for SPWF-based designs versus CMOS. In particular, for a 1-bit adder up to 40X area benefit and up to 304X power consumption reduction may be possible with SPWF-based implementation versus 45 nm CMOS.

Spin wave nanofabric update

We provide a progress update on the spin wave nanofabric. The nanofabric comprises magneto-electric cells and spin wave buses serving for spin wave propagation. The magneto-electric cells are used as the input/output ports for information transfer between the charge and the spin domains, while information processing inside the nanofabric is via spin waves only. Information is encoded into the phase of the propagating spin wave, which makes it possible to utilize waveguides as passive logic elements and take the advantage of using wave superposition for data processing. This provides a fundamental advantage over the conventional transistor-based logic circuitry allowing for functional throughput enhancement and power consumption minimization at the same time. We present recent accomplishments in the magneto-electric element development and integration with spin wave buses. In particular, we show the excitation and detection of the spin waves via multiferroic elements. In addition, we present different approaches to magnonic logic circuit engineering and provide the comparison with CMOS by mapping the designs to 45nm NANGATE standard cell libraries. The estimates show more than 40X power reduction and 53X area reduction for magnonic circuits. These results illustrate the potential advantages over conventional charge based electronics that could be a route to beyond CMOS logic circuitry.

Towards efficient on-chip sensor interconnect architecture for multi-core processors

With increasing number of cores in a SoC, the number of on-chip sensors to monitor temperature, voltage and soft errors is growing. Several researchers have suggested that even in multi-core/many-core era, the power and voltage management would still remain centralized. This necessitates an efficient channel to communicate sensor data towards the central control unhindered by the application data traffic or contending with it. Here, we propose an efficient fault tolerant tree based dedicated network to transmit the sensor data. Further, with the proposed architecture, router design becomes much simpler. Fault tolerance has been provided and synthesis results show that such fault tolerance is achieved at a very low area overhead ranging from 2.9% to 14.9% of the router area for the range of network parameters considered in this paper.

Post-CMOS hybrid spin-charge nanofabrics

We propose a hybrid spin-charge fabric with computation in spin domain and communication in charge domain. In nanofabrics based on non-equilibrium physical phenomenon like interference of spin waves, switching times are lower than the thermal relaxation times leading to fast multi-value logic at high fan-in without the exponential performance degradation noticeable in CMOS. While computation is much more efficient than in CMOS, these benefits can be lost due to the communication requirements between spin-wave blocks, when implemented with wave guides. This inspired a new type of hybrid nanofabric with spin wave high fan-in functions connected to an interconnect stack similar to CMOS: our analysis shows a delay reduction of up to 10X (8.64ns) along the critical path for a (511;9) parallel counter implemented in this fabric vs. spin-wave only. Similar benefits are also shown for a CLA adder with ∼4.2ns delay reduction for 1024 bit CLA adder.

Embedded processors based on Spin Wave Functions (SPWFs)

Spin Wave Functions (SPWFs) realize computation with spin waves, offering several benefits and new features over CMOS. SPWF technology potentially opens up new directions for designing microprocessors with increased capabilities over current implementations. Towards this end, as a preliminary work an 8-bit embedded processor is explored here using SPWFs and evaluated in terms of its power, area and performance using analytical estimates. A CMOS 8-bit processor implemented in an equivalent technology node is synthesized with CAD tools for comparison. Estimates show that the SPWF processor can have up to 40x lower power and 27× smaller area, thus showing great potential for realizing game-changing microprocessors in future.

Nanowire field-programmable computing platform

A nanowire-based field-programmable computing platform is presented featuring intrinsic fine-grained device-level reconfiguration without emulation (i.e. no look-up tables involved) using programmable cross-nanowire transistors, and regular physical implementation with relaxed manufacturing requirements at nanoscale. This approach can potentially provide orders of magnitude benefits in terms of area, power and performance vs. scaled CMOS FPGA at lower cost.