Santosh Koppa

A comparative analysis of coarse-grain and fine-grain power gating for FPGA lookup tables

Leakage power dissipation is becoming a concern in field-programmable gate arrays (FPGAs) due to scaling in FPGA technology. Widely available commercial FPGAs are based on lookup tables (LUTs) consisting of SRAM arrays and multiplexers. In this paper, we analyze the leakage power dissipation in the SRAM-array of a FPGA LUT for a 65nm CMOS process. We apply power-gating to an FPGA LUT SRAM array in two different ways, namely, coarse-grain power gating and fine-grain power gating. We carry out a comparative analysis of the two methods. In our research, we found that power-gating can be employed to drastically reduce the leakage power dissipation in the SRAM. More leakage savings were obtained with coarse-grain power-gating than with fine-grain power gating. The coarse-grain and fine-grain power-gating techniques yielded approximately 99 percent and 81 percent leakage savings, respectively, over the case where no power-gating is applied.

A 105.6dB DR and 65dB peak SNR self-reset CMOS image sensor using a Schmitt trigger circuit

A self-reset pixel level CMOS image sensor (CIS) is designed and tested which provides simultaneous improvements in dynamic-range (DR) and SNR performances. The pixel is fabricated in 0.5-µm 3-metal 2-poly CMOS technology and resulted in DR of 105.6dB with 65dB of peak SNR improvements. A simple Schmitt trigger circuit with offset cancellation technique is utilized to achieve this performance which compensates for the reset offset, comparator offset and reset delay.

Nanoscale biosensor chip

In this report, we demonstrate a nanoscale biosensor required for in field and fast detection. This sensor utilizes the Surface Plasmon Resonance (SPR) property of the gold nanorods of aspect ratio 5 to amplify the bio detection whose response is captured by three different photodiodes fabricated by the TSMC 0.18µm. Pinned photodiode yielded 176% and 80% higher response current than N+ diffusion/ P substrate (N+/psub) and N well/P substrate (NW/psub) diodes respectively. However NW/psub diode exhibited 1.5 and 6.7 times more sensitivity to 20nm shift in gold nanorod spectrum when compared to pinned and N+/psub diodes respectively.

A simple and robust self-reset CMOS image sensor

A simple and robust self-reset pixel-level CMOS image sensor (CIS) has been designed and tested to verify the improvement of the signal-to-noise ratio (SNR) compare to the conventional asynchronous self-reset pixel-level CISs. It significantly reduces noise accumulation from multiple self-resets by replacing a comparator and redundant regenerative modules with a simple Schmitt trigger circuit.

Topology selection of FPGA look-up tables for low-leakage operation

Modern field-programmable gate arrays (FPGAs) are increasingly becoming prone to leakage power dissipation, which can be attributed to their flexibility and increasing densities. One of the most important types of elements that are used throughout the FPGA fabric are the NMOS pass-transistor based multiplexers, which play a prominent role in both the logic and routing blocks. In this paper, we undertake a comparative study of various FPGA-LUT topologies that are based on different constituent multiplexers from a leakage power dissipation perspective, for a 45nm CMOS process. We found that a LUT constructed with two 8:1 decoded multiplexers or with three 4:1 multiplexers has lesser amount of leakage when compared to other topologies.

A quantitative performance analysis of FinFET based multiplier circuits

In this paper, we investigate and compare the performance of four different FinFET based multiplier topologies in terms of their leakage power, dynamic power, delay and power delay product at the transistor level. The multiplier topologies analyzed are Ripple Carry Array multiplier, Carry Save Array multiplier, Wallace Tree multiplier and Baugh-Wooley multiplier. The circuit simulations were performed in HSPICE using 20nm, and 14nm low-power FinFET models. 16×16 and 32×32 bit multiplier architectures were implemented for each topology. The results show that the Baugh-Wooley multiplier has the best power performance among all the multipliers investigated. The Wallace tree multiplier is the fastest among the all the multipliers for the 16×16 multiplier architecture. As the number of input bits increased, the Baugh-Wooley multiplier exhibited better power delay product. The results of this research is expected to provide a starting point for the design and analysis of more complex FinFET based circuits at transistor level.

An ultra-low power charge redistribution successive approximation register A/D converter for biomedical applications

Power consumption is one of the key design constraints in biomedical devices such as pacemakers that are powered by small non rechargeable batteries over their entire life time. In these systems, Analog to Digital Convertors (ADCs) are used as interface between analog world and digital domain and play a key role. In this paper we present the design of an 8-bit Charge Redistribution Successive Approximation Register (CR-SAR) analog to digital converter in standard TSMC 0.18μm CMOS technology for low power and low data rate devices such as pacemakers. The 8-bit optimized CR-SAR ADC achieves low power of less than 250nW with conversion rate of 1KB/s. This ADC achieves integral nonlinearity (INL) and differential nonlinearity (DNL) less than 0.22 least significant bit (LSB) and less than 0.04 LSB respectively as compared to the standard requirement for the INL and DNL errors to be less than 0.5 LSB. The designed ADC operates at 1V supply voltage converting input ranging from 0V to 250mV.

Improvised NanoSPR biosensor system utilizing gold nanorods and nanohole array film

A compact and sensitive biosensor device is proposed to detect the biomolecular interactions and bindings. This device arrangement utilizes natural white light to excite the Surface Plasmon Resonance (SPR) property of the gold nanorods which are utilized as the interface for the detection of molecular interactions. Gold nanohole array film with multiple periodicities is used to filter the response of the gold nanorods at different wavelengths which increases the sensitivity of the device by several folds. A high signal-to-noise ratio (SNR) CMOS image sensors (CIS) are used to detect the filtered output response. A comparative analysis of two different photodiodes namely pinned (pinn) and n well-p substrate (nwell-psub) photodiodes were used to compare the performance of the proposed nanoSPR system. System level simulation shows that the pinned photodiode had better performance compare to the nwell-psub photodiode.

Compact, low cost CMOS integrated SPR biosensor system

In this report, we propose a low cost, single chip, point of care CMOS integrated localized surface Plasmon resonance (LSPR) biosensor system. This system is composed of three unique functional layers in which two layers are integrated on to a single chip using conventional CMOS fabrication process to cut down the cost and improve the system sensitivity. Finite difference time domain (FDTD) simulations of nanohole array for before and after binding of antigen-antibody pairs gave a 10% change in the CMOS image sensor (CIS) response.