Youngjoong Joo

Fifth-derivative Gaussian pulse generator for UWB system

A noble pulse shaping method to generate an ultra wideband (UWB) pulse is designed and tested with the AMI 0.5-/spl mu/m CMOS process. The output pulse width is 2.4 ns, and the average power consumption is 1.159 mW with pulse repletion frequency (PRF) of 20 MHz. Test results show the feasibility of all digital low power UWB pulse generator design which complies with FCC regulations.

RTD/CMOS nanoelectronic circuits: thin-film InP-based resonant tunneling diodes integrated with CMOS circuits

The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 10/sup 6/ VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit.

Design of CMOS Scholtz's monocycle pulse generator

In this paper, a new Scholtzs monocycle pulse generator is proposed and simulated on TSMC 0.18 /spl mu/m CMOS technology. Scholtzs monocycle pulse, which has more advantages than the others, is basically achieved from second derivative of Gaussian pulse. Gaussian pulse is roughly achieved on quadrant squarer circuit with hyperbolic tangent input, and then Scholtzs monocycle pulse is generated by second differential operations in passive components. It can be applied to pulse generator in UWB transmitter as well as the wavelet for a correlator in receiver.

Ultra wideband CMOS low noise amplifier with active input matching

A new low noise amplifier (LNA) with broadband input matching and excellent gain flatness operating at the frequency range of 3.1-4.8 GHz is designed using a 0.18 /spl mu/m CMOS process. Wideband input matching using common-gate at the input stage is proposed. From a supply voltage of 1.8 V, the two-stage LNA exhibits a noise figure (NF) of 3.95-4.3 dB within the required bandwidth. The LNA has S11 less than -15 dB over the entire 3.1-4.8 GHz band. A reversed isolation (S12) less than -43 dB was achieved. A power gain (S21) of 16.5 dB with only 0.6 dB variations was obtained within the 3.1-4.8 GHz band. Input IP3 and 1 dB compression points are not of much concern in the case of the UWB LNA, since transmit power is restricted to be less than -42 dBm/Hz.

A Tunable CMOS UWB Pulse Generator

A tunable ultra-wideband (UWB) pulse generator is designed and simulated with standard 0.18 mum CMOS technology. By using a voltage controlled delay line (VCDL) technique, the proposed UWB pulse generator can adjust the pulse width, adding flexibility for use with different UWB applications. Moreover, each peak of the proposed UWB pulse is separately controlled so that it complies with the FCC regulation. The proposed UWB pulse generator achieves the fifth-order derivative of the Gaussian pulse and can tune the pulse width from 0.38-ns to 4-ns. In particular, the maximum and minimum pulse widths comply with 3-10 GHz and sub-GHz FCC regulations, respectively

Smart CMOS focal plane arrays: a Si CMOS detector array and sigma-delta analog-to-digital converter imaging system

This paper evaluates the potential for the real-time utilization of high frame rate image sequences using a fully parallel readout system. Multiple readout architectures for high frame rate imaging are compared. The application domain for a fully parallel readout system is identified, and the design for a fully parallel, monolithically integrated smart CMOS focal plane array is presented. This focal plane image processing chip, with an 8/spl times/8 array of Si CMOS detectors each of which have a dedicated on-chip current input first-order sigma-delta analog-to-digital converter front end, has been fabricated, and test results for uniformity and linearity are presented.

Microsystem optoelectronic integration for mixed multisignal systems

The integration and packaging of optoelectronic devices with electronic circuits and systems has growing application in many fields, ranging from long to micro haul links. An exploration of the opportunities, integration technologies, and some recent results using thin-film device heterogeneous integration with Si CMOS VLSI and GaAs MESFET circuit technologies are presented. Applications explored include alignment tolerant optoelectronic links for network interconnections, smart pixel focal plane array processing through the integration of imaging arrays with sigma delta analog to digital converters underneath each pixel, and three-dimensional computational systems using vertical through-Si optical interconnections.

Digitally controllable bi-phase CMOS UWB pulse generator

Digitally controllable bi-phase ultra wideband (UWB) pulse generator is designed with standard 0.18-/spl mu/m CMOS technology. Since the phase and amplitude of UWB pulse are digitally controlled, it is able to use bi-phase modulation and control the emission power with several pulse amplitudes. Assuming that FCC emission power limit is maximally used, the proposed pulse generator can be operated with pulse repetition frequency (PRF) of 77-MHz. The power consumption is maximally 1.88-mW and proportionally decreased as PRF is smaller. The proposed UWB pulse generator is a good candidate for a low-cost low-power impulse radio (IR).

Wide dynamic range and high SNR self-reset CMOS image sensor using a Schmitt trigger

A simple and robust self-reset image sensor design using Schmitt trigger circuit is presented. Offset and reset delay accumulations are compensated effectively so that a self-reset CMOS image sensor can exploit signal-to-noise ratio (SNR) improvement along with its wide dynamic range under multiple resets. It has been designed and simulated using 0.18 mum CMOS technology to show SNR improvement of 22.8 dB with 1000 self-resets. It also provides low power consumption and fewer components for pixel-level image sensor design.

Application of massively parallel processors to real time processing of high speed images

This paper demonstrates that the real-time utilization of image sequences, at frame rates far above what is currently possible, can now be achieved with an optically interconnected massively parallel processor. A focal plane processing chip with an on-chip array of sigma-delta analog to digital converter front ends under each pixel is presented. This two layer chip is a scaleable high frame rate image capture building block, however it requires a third layer of data processing to filter the sigma-delta front end data to obtain images. The use of an array of optically connected processors beneath the chip proves to be the best solution to this challenging data processing task.