Saori Kashiwada

Impact of ultra low power and fast write operation of advanced perpendicular MTJ on power reduction for high-performance mobile CPU

We demonstrated lower power consumption of mobile CPU by replacing high-performance (HP)-SRAMs with spin transfer torque (STT)-MRAMs using perpendicular (p)-MTJ. The key points that enable the low power consumption are adapting run time power gating architecture (shown in Fig. 1), and satisfying both fast and low-power writing, namely, 3 nsec and 0.09 pJ, of p-MTJ cell (shown in Fig. 3). As shown in Table 1, only our developed p-MTJ has achieved 3 nsec, 0.09 pJ. Thanks to the fast and low-power p-MTJ, the power consumption of cache memory could be reduced by over 80% without degradation of performance.

Circuit techniques in realizing voltage-generator-less STT MRAM suitable for normally-off-type non-volatile L2 cache memory

Circuit techniques for energy-efficient STT MRAM, which is suitable for replacing SRAM L2 cache memories, are proposed. The waking-up from the power-down mode without any cycle penalties becomes possible by eliminating the voltage generator even at higher frequency than 100MHz. The read current variation caused by the generator elimination is mitigated by 50% using the adaptive pulse-driven read current control. The cross-coupled hierarchical switch reduces the unneeded read current by 66% and enhances the read margin.

Sub-3 ns pulse with sub-100 µA switching of 1x–2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS

A novel perpendicular magnetic tunnel junction (MTJ) is developed that can be switched using pulse widths of around 1 ns and currents of less than 100 μA. This paper presents the first demonstration in novel achievement of fast switching, low power operation and size scalability of write current down to 16 nm diameter MTJ. This MTJ satisfies retention which is typically required in cache memory. Measurement results show that our proposed MTJ can open a path to embedded STT-MRAM in sub-20 nm CMOS generation.

1×- to 2×-nm MTJ switching at sub-3 ns pulses with compatible current in sub-20 nm CMOS for high performance embedded STT-MRAM

Magnetization switching was confirmed for sub-3-ns pulses below 100 µA in pMTJs down to 16 nm in diameter. The MR ratio exceeded 150%, satisfying requirements for fast read conditions. Using sub-30-nm MTJs, write-error rates of up to an order of −6 (10−6) were demonstrated. Read and write current margins, which were important device designs, were sufficiently large to avoid read disturbances. Moreover, 1×- to 2×-nm MTJs had sufficient data retention for level-2 or level-3 cache requirements. Furthermore, the MTJ resistance remained stable after 1012 write events. We believe these p-MTJs are potentially available for cache memory in sub-20-nm CMOS and reduce power consumption and while increasing cache capacity.