Daisuke Saida

Low power and high density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques

Since it has been difficult to increase clock frequency of processors due to power budget, there is a trend toward increase in number of processor cores and cache capacities (Fig. 1) to improve the processor performance. According to this trend, there have been two serious issues on the cache memories. One issue is large leakage power of SRAM-based cache (Ex. About 80% of average processor power in a mobile usage case [1]). Another one is large memory area of SRAM especially for last level cache (LLC) like L4 cache. Recently, eDRAM is used to reduce memory area for LLC (Fig. 1). However, gate length of eDRAM is difficult to be reduced less than 40-50 nm, and its power is not small due to frequent refresh (retention time ~ 100μs.). To reduce the cache power and decrease memory area further at the same time, advanced STT-MRAM based cache has been considered promising from theoretical analysis [2]. However, both low power and high density LLC have not been ever clarified based on a realistic MTJ (magnetic tunneling junction) integration and circuit design. This paper presents solutions for the power and memory density with more advanced STT-MRAM cell technologies by low-temperature process development and novel cache memory architecture based circuit design.

Circuit techniques in realizing voltage-generator-less STT MRAM suitable for normally-off-type non-volatile L2 cache memory

Circuit techniques for energy-efficient STT MRAM, which is suitable for replacing SRAM L2 cache memories, are proposed. The waking-up from the power-down mode without any cycle penalties becomes possible by eliminating the voltage generator even at higher frequency than 100MHz. The read current variation caused by the generator elimination is mitigated by 50% using the adaptive pulse-driven read current control. The cross-coupled hierarchical switch reduces the unneeded read current by 66% and enhances the read margin.

Low-Current High-Speed Spin-Transfer Switching in a Perpendicular Magnetic Tunnel Junction for Cache Memory in Mobile Processors

The efficiency of the power reduction in a normally off mobile processor employing spin-transfer torque magnetoresistive random access memory-based cache memory strongly depends on the write charge, which is the value of the write pulsewidth multiplied by the write current. We studied the spin-transfer switching probability (Psw) in a perpendicular magnetic tunnel junction (p-MTJ) with the aim of achieving high-speed switching of less than a few nanoseconds at a low current below 100 μA. High-speed switching faster than 1 ns was observed at a write current below 100 μA. To understand the observed pulsewidth dependence of Psw, analysis using a macrospin model based on a dynamic switching was carried out. The analysis reproduced the nature of the Psw distributions quantitatively. In addition, the developed analysis suggested the effectiveness of miniaturizing the storage layer to reduce the switching current. The p-MTJ operated continuously without any error at a write pulsewidth of 2 ns and current of 49 μA.

Magnetization states of a spin-torque oscillator having perpendicular polarizer and planar free layer

The dynamics and magnetization structures of spin-torque oscillators (STOs) consisting of a planar free layer and a perpendicular polarizer and having diameters of 10–100 nm are investigated by micromagnetic and macrospin simulations. For models having a diameter of 50 nm, the current-dependent frequency exhibited three oscillation modes: uniform oscillation, continuous oscillation with edge-localized core of the z-component of the magnetization (Mz component), and non-continuous rotation. The uniform oscillation mode and edge-localized oscillation mode are distinguished from each other by observing the frequencies of the Mz components. Further, we found that the oscillation frequency of the edge-localized mode changed in a step-like fashion under an external magnetic field, which was not observed in the uniform oscillation mode. The frequency in the edge-localized mode became saturated as the current increased toward the non-continuous mode, with the trajectory of the core gradually moving toward the cen...

Precise Damage Observation in Ion-Beam Etched MTJ

Patterning damage at the sidewall in a magnetic tunnel junction (MTJ) was observed precisely using a rectangular MTJ where deterioration in crystallinity is easier to identify than in the case of a dot-shaped conventional MTJ. A 200-500 nm-square rectangular MTJ was patterned by a 200 eV ion beam (IB). Cross-sectional transmission electron microscopy was used for damage observation. A bright-field image showed that crystallinity deteriorated to a depth of

MTJ-based "normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and last level cache based on 1T-1MTJ cell and novel error handling scheme

\sim 1.3

Sub-3 ns pulse with sub-100 µA switching of 1x–2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS

nm in the MgO-barrier layer. A Fourier transform mapping image and a dark-field transmission electron microscopy image indicated the existence of an amorphous region at the patterning edge in the MgO layer. IB etching is one of the strong candidates for magnetic random access memory (MRAM) fabrication. However, a typical IB etching energy, e.g., 200 eV, introduces a damage depth of several monolayers at the patterned surface. Since nearly damage-free-patterned surface would be needed for high-density MRAM with nanoscale MTJs of

1×- to 2×-nm MTJ switching at sub-3 ns pulses with compatible current in sub-20 nm CMOS for high performance embedded STT-MRAM

\sim 10

Effect of Ion-Beam Gas Species on Magnetic Softness in Fe-Co Thin-Film Etching

nm in diameter, IB etching with much lower energy would be necessary for fabrication.

MAGNETIC MEMORY ELEMENT

MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for high speed operation and considered not suited for lower level cache memory. In this work, we have developed L2 and L3 cache memory based on thermal stability factor engineered pMTJ with 2T-2MTJ and 1T-1MTJ memory cell and novel error handling scheme. These techniques reduce 75% energy with 2% performance overhead compared to SRAM-based l2 and L3 cache memory.