Chikayoshi Kamata

Impact of ultra low power and fast write operation of advanced perpendicular MTJ on power reduction for high-performance mobile CPU

We demonstrated lower power consumption of mobile CPU by replacing high-performance (HP)-SRAMs with spin transfer torque (STT)-MRAMs using perpendicular (p)-MTJ. The key points that enable the low power consumption are adapting run time power gating architecture (shown in Fig. 1), and satisfying both fast and low-power writing, namely, 3 nsec and 0.09 pJ, of p-MTJ cell (shown in Fig. 3). As shown in Table 1, only our developed p-MTJ has achieved 3 nsec, 0.09 pJ. Thanks to the fast and low-power p-MTJ, the power consumption of cache memory could be reduced by over 80% without degradation of performance.

Low power and high density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques

Since it has been difficult to increase clock frequency of processors due to power budget, there is a trend toward increase in number of processor cores and cache capacities (Fig. 1) to improve the processor performance. According to this trend, there have been two serious issues on the cache memories. One issue is large leakage power of SRAM-based cache (Ex. About 80% of average processor power in a mobile usage case [1]). Another one is large memory area of SRAM especially for last level cache (LLC) like L4 cache. Recently, eDRAM is used to reduce memory area for LLC (Fig. 1). However, gate length of eDRAM is difficult to be reduced less than 40-50 nm, and its power is not small due to frequent refresh (retention time ~ 100μs.). To reduce the cache power and decrease memory area further at the same time, advanced STT-MRAM based cache has been considered promising from theoretical analysis [2]. However, both low power and high density LLC have not been ever clarified based on a realistic MTJ (magnetic tunneling junction) integration and circuit design. This paper presents solutions for the power and memory density with more advanced STT-MRAM cell technologies by low-temperature process development and novel cache memory architecture based circuit design.

A 4ns, 0.9V write voltage embedded perpendicular STT-MRAM fabricated by MTJ-Last process

We evaluated embedded perpendicular spin transfer torque magnetic random access memory (STT-MRAM) performance fabricated by magnetic tunnel junction (MTJ) -“Last process”, which is able to expand material and structural design space of CMOS and MTJ, by SPICE simulation and test chip measurement. By the post-layout simulation, we show that the delay increase by parasitics, which originates from fabricating MTJ on the upper metal layer is below 50ps and negligible for most applications. And from the test chip measurement, we demonstrated switching operation as fast as 4ns, below 1V for STT-MRAM.

Circuit techniques in realizing voltage-generator-less STT MRAM suitable for normally-off-type non-volatile L2 cache memory

Circuit techniques for energy-efficient STT MRAM, which is suitable for replacing SRAM L2 cache memories, are proposed. The waking-up from the power-down mode without any cycle penalties becomes possible by eliminating the voltage generator even at higher frequency than 100MHz. The read current variation caused by the generator elimination is mitigated by 50% using the adaptive pulse-driven read current control. The cross-coupled hierarchical switch reduces the unneeded read current by 66% and enhances the read margin.

Low-Current High-Speed Spin-Transfer Switching in a Perpendicular Magnetic Tunnel Junction for Cache Memory in Mobile Processors

The efficiency of the power reduction in a normally off mobile processor employing spin-transfer torque magnetoresistive random access memory-based cache memory strongly depends on the write charge, which is the value of the write pulsewidth multiplied by the write current. We studied the spin-transfer switching probability (Psw) in a perpendicular magnetic tunnel junction (p-MTJ) with the aim of achieving high-speed switching of less than a few nanoseconds at a low current below 100 μA. High-speed switching faster than 1 ns was observed at a write current below 100 μA. To understand the observed pulsewidth dependence of Psw, analysis using a macrospin model based on a dynamic switching was carried out. The analysis reproduced the nature of the Psw distributions quantitatively. In addition, the developed analysis suggested the effectiveness of miniaturizing the storage layer to reduce the switching current. The p-MTJ operated continuously without any error at a write pulsewidth of 2 ns and current of 49 μA.

MTJ-based "normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and last level cache based on 1T-1MTJ cell and novel error handling scheme

MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for high speed operation and considered not suited for lower level cache memory. In this work, we have developed L2 and L3 cache memory based on thermal stability factor engineered pMTJ with 2T-2MTJ and 1T-1MTJ memory cell and novel error handling scheme. These techniques reduce 75% energy with 2% performance overhead compared to SRAM-based l2 and L3 cache memory.