Sapan Agarwal

A non-volatile organic electrochemical device as a low-voltage artificial synapse for neuromorphic computing

The brain is capable of massively parallel information processing while consuming only ∼1-100 fJ per synaptic event. Inspired by the efficiency of the brain, CMOS-based neural architectures and memristors are being developed for pattern recognition and machine learning. However, the volatility, design complexity and high supply voltages for CMOS architectures, and the stochastic and energy-costly switching of memristors complicate the path to achieve the interconnectivity, information density, and energy efficiency of the brain using either approach. Here we describe an electrochemical neuromorphic organic device (ENODe) operating with a fundamentally different mechanism from existing memristors. ENODe switches at low voltage and energy (<10 pJ for 103 μm2 devices), displays >500 distinct, non-volatile conductance states within a ∼1 V range, and achieves high classification accuracy when implemented in neural network simulations. Plastic ENODes are also fabricated on flexible substrates enabling the integration of neuromorphic functionality in stretchable electronic systems. Mechanical flexibility makes ENODes compatible with three-dimensional architectures, opening a path towards extreme interconnectivity comparable to the human brain.

Tunnel Field Effect Transistor With Raised Germanium Source

The performance of a tunnel field effect transistor (TFET) with a raised germanium (Ge) source region is investigated via 2-D device simulation with a tunneling model calibrated to experimental data. The comparison of various Ge-source TFET designs shows that a fully elevated Ge-source design provides for the steepest subthreshold swing and, therefore, the largest on-state drive current for low-voltage operation. Mixed-mode (dc and ac) simulations are used to assess the energy-delay performance. In comparison with a MOSFET, an optimized Ge-source TFET is projected to provide for a lower energy per operation for throughput in the frequency range of up to ~1 GHz for sub-0.5-V operation.

Band-Edge Steepness Obtained From Esaki/Backward Diode Current–Voltage Characteristics

While science has good knowledge of semiconductor bandgaps, there is not much information regarding the steepness of the band edges. We find that a plot of absolute conductance, I/V versus voltage V , in an Esaki diode or a backward diode will reveal a best limit for the band tails, defined by the tunneling joint density of states of the two band edges. This joint density of states will give information about the prospective subthreshold swing voltage that could be expected in a tunneling field-effect transistor. To date, published current-voltage characteristics indicate that the joint band-tail density of states is not steep enough to achieve <;60 mV/decade. Heavy doping inhomogeneity, among other inhomogeneities, results in a gradual density of states extending into the bandgap. The steepest measured tunnel diodes have a tunneling joint density of states >90 mV/decade.

Using dimensionality to achieve a sharp tunneling FET (TFET) turn-on

In order to achieve significantly reduced power consumption, the transistor operating voltage needs to be reduced. To do this, a tunneling based transistor needs to rely on the density of states turn-on as shown in Fig 1 [1]. Current can only flow when the conduction and valence bands overlap. If the band edges are ideal, one might expect an infinitely sharp turn on when the band edges overlap. Surprisingly, in a typical 3d bulk TFET, the nature of the turn on is actually quadratic in the gate voltage. Nevertheless, it is possible improve this if dimensionality is reduced. Consequently, we explored the nature of the band overlap for the various dimensionalities shown in Fig 2. We find that a 2d-2d pn junction, as shown in Fig. 2(i) brings us significantly closer to an ideal step function. Confining each side of the pn junction will also significantly increase the on state conductivity at low voltages.

Impact of Quantization Energy and Gate Leakage in Bilayer Tunneling Transistors

The effect of quantum mechanical confinement in recently proposed thin-body double-gate electron-hole bilayer tunneling transistors is examined. In such devices, a vertical electric field, which is produced by oppositely biased double gates, induces vertical band-to-band tunneling across the intrinsic semiconductor channel. It is found that reducing body thickness in order to increase tunneling probability, i.e., source-drain current drive, considerably increases confinement energy, requiring a large gate and semiconductor electric field, and therefore voltage, to reach electron and hole eigenstate alignment. Furthermore, large electric fields across the gate dielectrics are expected to cause substantial gate leakage current. Design limits based on this analysis are discussed.

Engineering the Electron–Hole Bilayer Tunneling Field-Effect Transistor

The electron-hole (EH) bilayer tunneling field-effect transistor promises to eliminate heavy-doping band tails enabling a smaller subthreshold swing voltage. Nevertheless, the electrostatics of a thin structure must be optimized for gate efficiency. We analyze the tradeoff between gate efficiency versus ON-state conductance to find the optimal device design. Once the EH bilayer is optimized for a given ON-state conductance, Si, Ge, and InAs all have similar gate efficiency, around 40%-50%. Unlike Si and Ge, only the InAs case allows a manageable work function difference for EH bilayer transistor operation.

Energy Scaling Advantages of Resistive Memory Crossbar Based Computation and Its Application to Sparse Coding

The exponential increase in data over the last decade presents a significant challenge to analytics efforts that seek to process and interpret such data for various applications. Neural-inspired computing approaches are being developed in order to leverage the computational properties of the analog, low-power data processing observed in biological systems. Analog resistive memory crossbars can perform a parallel read or a vector-matrix multiplication as well as a parallel write or a rank-1 update with high computational efficiency. For an N × N crossbar, these two kernels can be O(N) more energy efficient than a conventional digital memory-based architecture. If the read operation is noise limited, the energy to read a column can be independent of the crossbar size (O(1)). These two kernels form the basis of many neuromorphic algorithms such as image, text, and speech recognition. For instance, these kernels can be applied to a neural sparse coding algorithm to give an O(N) reduction in energy for the entire algorithm when run with finite precision. Sparse coding is a rich problem with a host of applications including computer vision, object tracking, and more generally unsupervised learning.

Resistive memory device requirements for a neural algorithm accelerator.

Resistive memories enable dramatic energy reductions for neural algorithms. We propose a general purpose neural architecture that can accelerate many different algorithms and determine the device properties that will be needed to run backpropagation on the neural architecture. To maintain high accuracy, the read noise standard deviation should be less than 5% of the weight range. The write noise standard deviation should be less than 0.4% of the weight range and up to 300% of a characteristic update (for the datasets tested). Asymmetric nonlinearities in the change in conductance vs pulse cause weight decay and significantly reduce the accuracy, while moderate symmetric nonlinearities do not have an effect. In order to allow for parallel reads and writes the write current should be less than 100 nA as well.

Auger Generation as an Intrinsic Limit to Tunneling Field-Effect Transistor Performance

Many in the microelectronics field view tunneling field-effect transistors (TFETs) as societys best hope for achieving a >10× power reduction for electronic devices; however, despite a decade of considerable worldwide research, experimental TFET results have significantly underperformed simulations and conventional MOSFETs. To explain the discrepancy between TFET experiments and simulations, we investigate the parasitic leakage current due to Auger generation, an intrinsic mechanism that cannot be mitigated with improved material quality or better device processing. We expose the intrinsic link between the Auger and band-to-band tunneling rates, highlighting the difficulty of increasing one without the other. From this link, we show that Auger generation imposes a fundamental limit on ultimate TFET performance.

Neuromemristive Systems: Boosting Efficiency through Brain-Inspired Computing

Neuromemristive systems (NMSs) are gaining traction as an alternative to conventional CMOS-based von Neumann systems because of their greater energy and area efficiency. A proposed NMS accelerator for machine-learning tasks reduced power dissipation by five orders of magnitude, relative to a multicore reduced-instruction set computing processor.