Saptarshi Das

High Performance Multilayer MoS2 Transistors with Scandium Contacts

While there has been growing interest in two-dimensional (2-D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancy due to the lack of a complete picture of their performance potential. The focus of this article is on contacts. We demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS(2) layers the excellent intrinsic properties of this 2-D material can be harvested. Using scandium contacts on 10-nm-thick exfoliated MoS(2) flakes that are covered by a 15 nm Al(2)O(3) film, high effective mobilities of 700 cm(2)/(V s) are achieved at room temperature. This breakthrough is largely attributed to the fact that we succeeded in eliminating contact resistance effects that limited the device performance in the past unrecognized. In fact, the apparent linear dependence of current on drain voltage had mislead researchers to believe that a truly Ohmic contact had already been achieved, a misconception that we also elucidate in the present article.

Tunable Transport Gap in Phosphorene

In this article, we experimentally demonstrate that the transport gap of phosphorene can be tuned monotonically from ∼0.3 to ∼1.0 eV when the flake thickness is scaled down from bulk to a single layer. As a consequence, the ON current, the OFF current, and the current ON/OFF ratios of phosphorene field effect transistors (FETs) were found to be significantly impacted by the layer thickness. The transport gap was determined from the transfer characteristics of phosphorene FETs using a robust technique that has not been reported before. The detailed mathematical model is also provided. By scaling the thickness of the gate oxide, we were also able to demonstrate enhanced ambipolar conduction in monolayer and few layer phosphorene FETs. The asymmetry of the electron and the hole current was found to be dependent on the layer thickness that can be explained by dynamic changes of the metal Fermi level with the energy band of phosphorene depending on the layer number. We also extracted the Schottky barrier heights for both the electron and the hole injection as a function of the layer thickness. Finally, we discuss the dependence of field effect hole mobility of phosphorene on temperature and carrier concentration.

Ambipolar phosphorene field effect transistor.

In this article, we demonstrate enhanced electron and hole transport in few-layer phosphorene field effect transistors (FETs) using titanium as the source/drain contact electrode and 20 nm SiO2 as the back gate dielectric. The field effect mobility values were extracted to be ∼38 cm(2)/Vs for electrons and ∼172 cm(2)/Vs for the holes. On the basis of our experimental data, we also comprehensively discuss how the contact resistances arising due to the Schottky barriers at the source and the drain end effect the different regime of the device characteristics and ultimately limit the ON state performance. We also propose and implement a novel technique for extracting the transport gap as well as the Schottky barrier height at the metal-phosphorene contact interface from the ambipolar transfer characteristics of the phosphorene FETs. This robust technique is applicable to any ultrathin body semiconductor which demonstrates symmetric ambipolar conduction. Finally, we demonstrate a high gain, high noise margin, chemical doping free, and fully complementary logic inverter based on ambipolar phosphorene FETs.

All Two-Dimensional, Flexible, Transparent, and Thinnest Thin Film Transistor

In this article, we report only 10 atomic layer thick, high mobility, transparent thin film transistors (TFTs) with ambipolar device characteristics fabricated on both a conventional silicon platform as well as on a flexible substrate. Monolayer graphene was used as metal electrodes, 3-4 atomic layers of h-BN were used as the gate dielectric, and finally bilayers of WSe2 were used as the semiconducting channel material for the TFTs. The field effect carrier mobility was extracted to be 45 cm(2)/(V s), which exceeds the mobility values of state of the art amorphous silicon based TFTs by ∼100 times. The active device stack of WSe2-hBN-graphene was found to be more than 88% transparent over the entire visible spectrum and the device characteristics were unaltered for in-plane mechanical strain of up to 2%. The device demonstrated remarkable temperature stability over 77-400 K. Low contact resistance value of 1.4 kΩ-μm, subthreshold slope of 90 mv/decade, current ON-OFF ratio of 10(7), and presence of both electron and hole conduction were observed in our all two-dimensional (2D) TFTs, which are extremely desirable but rarely reported characteristics of most of the organic and inorganic TFTs. To the best of our knowledge, this is the first report of all 2D transparent TFT fabricated on flexible substrate along with the highest mobility and current ON-OFF ratio.

WSe2 field effect transistors with enhanced ambipolar characteristics

One of the most relevant features that a semiconducting channel material can offer when used in a field-effect transistor (FET) layout is its capability to enable both electron transport in the conduction band and hole transport in the valence band. In this way, complementary metal-oxide-semiconductor type applications become feasible once similar electron and hole drive current densities are achieved, and the threshold voltages are properly adjusted. In this article, we demonstrate pronounced ambipolar device characteristics of multilayer WSe2 FETs using different contact electrodes. Our study reveals that nickel electrodes facilitate electron injection while palladium electrodes are more efficient for hole injection. We also show, as an interesting demonstration, that by using nickel as the source contact electrode and palladium as the drain contact electrode, ambipolar device characteristics with similar on-state performance for both the electron and the hole branch can be achieved in WSe2 FETs. Finall...

Toward low-power electronics: tunneling phenomena in transition metal dichalcogenides.

In this article, we explore, experimentally, the impact of band-to-band tunneling on the electronic transport of double-gated WSe2 field-effect transistors (FETs) and Schottky barrier tunneling of holes in back-gated MoS2 FETs. We show that by scaling the flake thickness and the thickness of the gate oxide, the tunneling current can be increased by several orders of magnitude. We also perform numerical calculations based on Landauer formalism and WKB approximation to explain our experimental findings. Based on our simple model, we discuss the impact of band gap and effective mass on the band-to-band tunneling current and evaluate the performance limits for a set of dichalcogenides in the context of tunneling transistors for low-power applications. Our findings suggest that WTe2 is an excellent choice for tunneling field-effect transistors.

FETRAM. An Organic Ferroelectric Material Based Novel Random Access Memory Cell

Science and technology in the electronics area have always been driven by the development of materials with unique properties and their integration into novel device concepts with the ultimate goal to enable new functionalities in innovative circuit architectures. In particular, a shift in paradigm requires a synergistic approach that combines materials, devices and circuit aspects simultaneously. Here we report the experimental implementation of a novel nonvolatile memory cell that combines silicon nanowires with an organic ferroelectric polymer-PVDF-TrFE-into a new ferroelectric transistor architecture. Our new cell, the ferroelectric transistor random access memory (FeTRAM) exhibits similarities with state-of-the-art ferroelectric random access memories (FeRAMs) in that it utilizes a ferroelectric material to store information in a nonvolatile (NV) fashion but with the added advantage of allowing for nondestructive readout. This nondestructive readout is a result of information being stored in our cell using a ferroelectric transistor instead of a capacitor-the scheme commonly employed in conventional FeRAMs.

High gain, low noise, fully complementary logic inverter based on bi-layer WSe2 field effect transistors

In this article, first, we show that by contact work function engineering, electrostatic doping and proper scaling of both the oxide thickness and the flake thickness, high performance p- and n-type WSe2 field effect transistors (FETs) can be realized. We report record high drive current of 98 μA/μm for the electron conduction and 110 μA/μm for the hole conduction in Schottky barrier WSe2 FETs. Then, we combine high performance WSe2 PFET with WSe2 NFET in double gated transistor geometry to demonstrate a fully complementary logic inverter. We also show that by adjusting the threshold voltages for the NFET and the PFET, the gain and the noise margin of the inverter can be significantly enhanced. The maximum gain of our chemical doping free WSe2 inverter was found to be ∼25 and the noise margin was close to its ideal value of ∼2.5 V for a supply voltage of VDD = 5.0 V.

Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser Annealing

We have experimentally established that the inverse subthreshold slope S of a Si nanowire tunneling field-effect transistor (NW-TFET) array can be within 9% of the theoretical limit when the doping profile along the channel is properly engineered. In particular, we have demonstrated that combining excimer laser annealing with a low-temperature rapid thermal anneal results in an abrupt doping profile at the source/channel interface as evidenced by the electrical characteristics. Gate-controlled tunneling has been confirmed by evaluating S as a function of temperature. The good agreement between our experimental data and simulation allows performance predictions for more aggressively scaled TFETs. We find that Si NW-TFETs can be indeed expected to deliver S-values below 60 mV/dec for optimized device structures.

The significance of a correlation of blister diameter with skin thickness for Ni and Be for blistering models

It has been suggested that large lateral stresses introduced in an ion implanted surface layer may cause elastic instability and buckling of the implant layer (blister formation), and result in a relationship D/sub mp/ varies as t/sup 3///sup 2/ between the most probable blister diameter D/sub mp/ and the blister skin thickness, t, for metals such as Be, V, stainless steel, Nb and Mo. To test this relationship a systematic study of the correlation between blister diameter and skin thickness for helium blistering of annealed polycrystalline Ni and Be has been conducted for helium ion energies in the range of 15-300 keV. For beryllium the relationship between D/sub mp/ (..mu..m) and t(..mu..m) can be fitted by the expression D/sub mp/ = 24.6t/sup 1/./sup 25/ whereas for nickel a best fit is obtained for the expression D/sub mp/ = 1.24t/sup 1/./sup 15/. These results, together with our earlier results for Nb and V, show that the relationship between D/sub mp/ and t is strongly dependent on the type of metal studied and do not support the lateral stress model for blister formation.