Sara dos Santos
University of São Paulo
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Publication
Featured researches published by Sara dos Santos.
IEEE Electron Device Letters | 2012
Talitha Nicoletti; Marc Aoulaiche; Luciano M. Almeida; Sara dos Santos; J. A. Martino; A. Veloso; Malgorzata Jurczak; Eddy Simoen; Cor Claeys
The floating-body-RAM sense margin and retention-time dependence on the gate length is investigated in UTBOX devices using BJT programming combined with a positive back bias (so-called V th feedback). It is shown that the sense margin and the retention time can be kept constant versus the gate length by using a positive back bias. Nevertheless, below a critical L, there is no room for optimization, and the memory performances suddenly drop. The mechanism behind this degradation is attributed to GIDL current amplification by the lateral bipolar transistor with a narrow base. The gate length can be further scaled using underlap junctions.
IEEE Transactions on Electron Devices | 2013
Sara dos Santos; Talitha Nicoletti; J. A. Martino; Marc Aoulaiche; A. Veloso; Malgorzata Jurczak; Eddy Simoen; Cor Claeys
The low-frequency noise has been studied in ultrathin-buried-oxide silicon-on-insulator nMOSFETs, analyzing the impact of different silicon film thicknesses and the front-/back-channel coupling. Significant device-to-device spread has been observed in the noise performance as well as in Vth and μN features, pointing out the influence of a nonuniform silicon film thickness that also affects the quality of the Si/SiO2 interface. The occurrence of generation-recombination centers has been ascribed to traps present not only in the silicon film but also in the front/back oxide since the Fermi level can be swept over a large fraction of the band gap, owing to the higher electrical coupling between both interfaces.
IEEE Transactions on Electron Devices | 2015
Paula Ghedini Der Agopian; Marcio D. V. Martino; Sara dos Santos; Felipe Lucas da Silva Neves; Joao Antonio Martino; Rita Rooyackers; Anne Vandooren; Eddy Simoen; Aaron Thean; Cor Claeys
The goal of this paper is to study the analog performance parameters of tunnel field-effect transistors (TFETs) with different source compositions and process conditions. The experimental matrix included devices with either a 100% silicon or Si1-xGex source, so that the germanium amount at the source/channel interface could be correlated with the prevailing transport mechanism and its impact on transconductance (gm), output conductance (gDS), and early voltage (VEA) could be analyzed. The used process conditions were highlighted by comparing a reference split with no Si passivation to the cases with 12 and 18 Si monolayers to determine their influence on the interface trap density and eventual reduction of the traps in the gate oxide. All these process parameters enable to make conclusions on the intrinsic voltage gain (AV) and the low-frequency noise. Based on these results, the suitability of each type of TFET has been discussed, revealing that 100% Si may still be considered
international conference on ultimate integration on silicon | 2012
Talitha Nicoletti; Sara dos Santos; Luciano M. Almeida; J. A. Martino; Marc Aoulaiche; A. Veloso; Malgorzata Jurczak; Eddy Simoen; Cor Claeys
In this paper we explore, from DC measurements, the impact of gate length scaling on the main digital/analog parameters of Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon-on-Insulator (FDSOI) devices at different temperatures. Standard junction reference devices are compared with the extension-less ones where the latter present superior characteristics for smaller device lengths such as improved DIBL, SS and IGIDL apart from the higher Ion/Ioff ratio, VEA and AV. The temperature tends to degrade all the device parameters although the extension-less structures show to be less susceptible to its influence.
Physica Status Solidi (c) | 2015
Eddy Simoen; Bogdan Cretu; Wen Fang; Marc Aoulaiche; Jean-Marc Routoure; Regis Carin; Sara dos Santos; Jun Luo; Chao Zhao; J. Martino; Cor Claeys
An overview is given on the possibilities of using generation-recombination (GR) noise as a tool for defect spectroscopy in semiconductor materials and devices. The method is illustrated by n-channel MOSFETs fabricated on silicon-on-insulator (SOI) substrates with an ultra-thin buried oxide (UTBOX). As will be shown, the use of fully depleted (FD) UTBOX devices offers some unique opportunities and challenges. In the first instance, one can apply the standard GR noise spectroscopy in function of the temperature to derive the relevant deep-level parameters like the activation energy, the capture cross section and the concentration. In addition, some new type of spectroscopy can be applied to defects in the silicon film by exploiting the front- and/or back-gate bias dependence of the Lorentzian noise parameters. Finally, it is shown that for small geometry transistors the GR noise is generated by one or only a few centres. This becomes obvious in the time domain, where the channel current exhibits random telegraph signal (RTS) fluctuations. The up and down time constants and the relative RTS amplitude can be used to derive the GR centre parameters and, moreover, its spatial location, when combined with numerical device simulations. (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)
international soi conference | 2012
Talitha Nicoletti; Sara dos Santos; J. A. Martino; Marc Aoulaiche; A. Veloso; Malgorzata Jurczak; Eddy Simoen; Cor Claeys
FBRAM on UTBOX SOI wafers, using the BJT with a positive back bias programming scheme, is studied versus the gate length. The optimized FBRAM parameters such as the sense margin and the retention time are shown as a function of the gate length. For longer L the back bias can be used to optimize the FBRAM performance, whereas for shorter L, hole generation amplification during the read operation by the bipolar junction transistor gain, inherent to SOI nMOSFET devices and used for the read is a limiting issue. Therefore, there is critical gate length to FBRAM scaling. To avoid FBRAM performance degradation, L should be longer than the critical length. Moreover, this work suggests that vertical devices, which allow longer L are more scalable.
ieee soi 3d subthreshold microelectronics technology unified conference | 2013
Talitha Nicoletti; Sara dos Santos; Katia Regina Akemi Sasaki; J. A. Martino; Marc Aoulaiche; Eddy Simoen; Cor Claeys
The dependence of the activation energy on the electric field is investigated in extensionless (underlap) UTBOX FDSOI applied as a single transistor floating body RAM. It was found that with the same gate stack it is possible to extract two different activation energies when the electric field in the hold condition is different. Higher barrier lowering induced by elevated electric field implies in higher energy trap level. The dominant mechanism behind this dependence is identified and attributed to Poole-Frenkel effect.
symposium on microelectronics technology and devices | 2011
Sara dos Santos; Talitha Nicoletti; J.A Martino
Journal of Integrated Circuits and Systems | 2010
Sara dos Santos; Joao Antonio Martino; Eddy Simoen; Cor Claeys; Luciano Gualberto
symposium on microelectronics technology and devices | 2012
Sara dos Santos; Talitha Nicoletti; Marc Aoulaiche; J. A. Martino; A. Veloso; Malgorzata Jurczak; Eddy Simoen; Cor Claeys