J. A. Martino

The Dependence of Retention Time on Gate Length in UTBOX FBRAM With Different Source/Drain Junction Engineering

The floating-body-RAM sense margin and retention-time dependence on the gate length is investigated in UTBOX devices using BJT programming combined with a positive back bias (so-called V th feedback). It is shown that the sense margin and the retention time can be kept constant versus the gate length by using a positive back bias. Nevertheless, below a critical L, there is no room for optimization, and the memory performances suddenly drop. The mechanism behind this degradation is attributed to GIDL current amplification by the lateral bipolar transistor with a narrow base. The gate length can be further scaled using underlap junctions.

On the Variability of the Front-/Back-Channel LF Noise in UTBOX SOI nMOSFETs

The low-frequency noise has been studied in ultrathin-buried-oxide silicon-on-insulator nMOSFETs, analyzing the impact of different silicon film thicknesses and the front-/back-channel coupling. Significant device-to-device spread has been observed in the noise performance as well as in Vth and μN features, pointing out the influence of a nonuniform silicon film thickness that also affects the quality of the Si/SiO2 interface. The occurrence of generation-recombination centers has been ascribed to traps present not only in the silicon film but also in the front/back oxide since the Fermi level can be swept over a large fraction of the band gap, owing to the higher electrical coupling between both interfaces.

The impact of gate length scaling on UTBOX FDSOI devices: The digital/analog performance of extension-less structures

In this paper we explore, from DC measurements, the impact of gate length scaling on the main digital/analog parameters of Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon-on-Insulator (FDSOI) devices at different temperatures. Standard junction reference devices are compared with the extension-less ones where the latter present superior characteristics for smaller device lengths such as improved DIBL, SS and IGIDL apart from the higher Ion/Ioff ratio, VEA and AV. The temperature tends to degrade all the device parameters although the extension-less structures show to be less susceptible to its influence.

Gate length impact on UTBOX FBRAM devices

FBRAM on UTBOX SOI wafers, using the BJT with a positive back bias programming scheme, is studied versus the gate length. The optimized FBRAM parameters such as the sense margin and the retention time are shown as a function of the gate length. For longer L the back bias can be used to optimize the FBRAM performance, whereas for shorter L, hole generation amplification during the read operation by the bipolar junction transistor gain, inherent to SOI nMOSFET devices and used for the read is a limiting issue. Therefore, there is critical gate length to FBRAM scaling. To avoid FBRAM performance degradation, L should be longer than the critical length. Moreover, this work suggests that vertical devices, which allow longer L are more scalable.

The activation energy dependence on the electric field in UTBOX SOI FBRAM devices

The dependence of the activation energy on the electric field is investigated in extensionless (underlap) UTBOX FDSOI applied as a single transistor floating body RAM. It was found that with the same gate stack it is possible to extract two different activation energies when the electric field in the hold condition is different. Higher barrier lowering induced by elevated electric field implies in higher energy trap level. The dominant mechanism behind this dependence is identified and attributed to Poole-Frenkel effect.