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Sarah E. Kim

Intel

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Publication

Featured researches published by Sarah E. Kim.

Archive | 2004

Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices

Sarah E. Kim; R. Scott List; Scot A. Kellar

Archive | 2003

Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack

Scot A. Kellar; Sarah E. Kim; R. Scott List

Archive | 2005

3D integrated circuits using thick metal for backside connections and offset bumps

Shriram Ramanathan; Sarah E. Kim; Patrick Morrow

Archive | 2002

Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same

Scot A. Kellar; Sarah E. Kim; R. Scott List

Archive | 2002

Thinning techniques for wafer-to-wafer vertical stacks

Sarah E. Kim; R. Scott List; Mauro J. Kobrinsky

Archive | 2002

Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof

Scot A. Kellar; Sarah E. Kim; R. Scott List

Archive | 2003

Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration

Scot A. Kellar; Sarah E. Kim; R. Scott List

Archive | 2005

Methods of forming backside connections on a wafer stack

Patrick Morrow; R. Scott List; Sarah E. Kim

Archive | 2003

Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack

Sarah E. Kim; R. Scott List; Tom Letson

Archive | 2005

Ultra-high capacitance device based on nanostructures

Scot A. Kellar; Sarah E. Kim

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Collaboration

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R. Scott List

Intel

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Scot A. Kellar

Intel

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Alan Myers

Intel

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James G. Maveety

Intel

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Quat T. Vu

Intel

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Mauro J. Kobrinsky

Intel

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Patrick Morrow

Intel

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M. Harmes

Intel

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Shriram Ramanathan

Harvard University

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Bruce A. Block

Intel

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