Patrick Morrow

Die Stacking (3D) Microarchitecture

3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die stacking is a significant reduction of interconnect both within a die and across dies in a system. For instance, blocks within a microprocessor can be placed vertically on multiple die to reduce block to block wire distance, latency, and power. Disparate Si technologies can also be combined in a 3D die stack, such as DRAM stacked on a CPU, resulting in lower power higher BW and lower latency interfaces, without concern for technology integration into a single process flow. 3D has the potential to change processor design constraints by providing substantial power and performance benefits. Despite the promising advantages of 3D, there is significant concern for thermal impact. In this research, we study the performance advantages and thermal challenges of two forms of die stacking: Stacking a large DRAM or SRAM cache on a microprocessor and dividing a traditional micro architecture between two die in a stack

Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

The authors report the first demonstration of integrating wafer stacking via Cu bonding with strained-Si/low-k 65-nm CMOS technology. Sets of 330 mm wafers with active devices such as 65-nm MOSFETs and 4-MB SRAMs were bonded face-to-face using copper pads with size ranging between 5 /spl mu/m/spl times/5 /spl mu/m and 6 /spl mu/m/spl times/40 /spl mu/m. The top wafers were thinned to different thicknesses in the range 5 to 28 /spl mu/m. Through-silicon-vias (TSVs) and backside metallization were used to enable electrical testing of both wafers in the Cu-stacked configuration. We tested individual transistors in the thinned silicon of bonded wafer pairs where the thinned silicon thickness ranged from 14 to 19 /spl mu/m. All results showed that both n- and p-channel transistors preserved their electrical characteristics after Cu bonding, thinning, and TSV integration. We also demonstrated the functionality of stacked 65-nm 4-MB SRAMs by independently testing the cells in both the thinned wafer and the bottom wafer. For the SRAM, we tested a wider thinned wafer thickness range from 5 to 28 /spl mu/m. On all tested samples, we did not find any impact to the electrical performance of the arrays resulting from the three-dimensional (3-D) integration process. The stacked SRAM is an experimental demonstration of the use of 3-D integration to effectively double transistor packing density for the same planar footprint. The results presented in this letter enable further exploratory work in high-performance 3-D logic, which takes advantage of the improved interconnect delays offered by this Cu-bonding stacking scheme integrated with modern CMOS processes.

Design and Fabrication of 3D Microprocessors

Stacking multiple device strata can improve system performance of a microprocessor (μP) by reducing interconnect length. This enables latency improvement, power reduction, and improved memory bandwidth. In this paper we review some of our recent design analysis and process results which quantitatively show the benefits of stacking applied to μPs. We report on two applications for stacking which take advantage of reduced wire length- “logic+logic” stacking and “logic+memory” stacking. In addition to optimizing minimum wire length, we considered carefully the thermal ramifications of the new designs. For the logic+memory application, we considered the case of reducing off-die wiring by stacking a DRAM cache (32 to 64MB) onto a high performance μP. Simulations showed 3x reduced off-die bandwidth, Cycles Per Memory Access (CPMA) reduction of 13%, and a 66% average bus power reduction. For logic+logic applications, we considered a high performance μP where the unit blocks were repartitioned into two strata. For this case, simulations showed that stacking can simultaneously reduce power by 15% while increasing performance by 15% with a minor 14° C increase in peak temperature compared to the planar design. Using voltage scaling, this translates to 34% power reduction and 8% performance improvement with no temperature increase. We found that these results can be further improved by a secondary splitting of the individual blocks. As an example, we split a 32KB first level data cache resulting in 25% power reduction, 10% latency reduction, and 20% area reduction. We also discuss the fabrication of stacked structures with two complimentary process flows. In one case, we developed a 300mm wafer stacking process using Cu-Cu bonding, wafer thinning, and through-silicon vias (TSVs). This technology provides reliable bonding with non-detectable bonding-interface resistance and inter-strata via pitch below 8μm. We investigated the impact of this wafer stacking process to the transistor and interconnect layers built using a 65nm strained-Si/Cu-Low-K process technology and found no impact to either discrete N- and P-MOS devices or to thin 4Mb SRAMs. We verified fully functional SRAMs on thinned wafers with thicknesses down to 5μm. Although wafer stacking leads itself well to tight-pitch same-die-size stacking, die stacking enables integration of different size dies and includes opportunity to improve yield by stacking known good dies. We demonstrated a die stack process flow with 75μm thinned die, TSV, and inter-strata via pitch below 100μm. We also found negligible impact to transistors using this process flow. Multiple stacks of up to seven 75μm thin dies with TSVs were fabricated and tested. Prospects for high volume integration of 3D into μPs are discussed.

Ultra high density logic designs using transistor-level monolithic 3D integration

Recent innovations in monolithic 3D technology enable much higher-density vertical connections than todays through-silicon-via (TSV)-based technology. In this paper, we investigate the benefits and challenges of monolithic 3D integration technology for ultra high-density logic designs. Based on our layout experiments, we compare important design metrics such as area, wirelength, timing, and power consumption of monolithic 3D designs with the traditional 2D designs. We also explore various interconnect options for monolithic 3D ICs that improve design density and quality. Depending on the interconnect settings of monolithic 3D ICs and the benchmark circuit characteristics, we observe that our two-tier monolithic 3D design provides up to 40% reduced footprint, 27.7% shorter wirelength, 39.7% faster operation, and 9.7% lower power consumption over the 2D counterpart.

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core

Low power is considered by many as the driving force for 3D ICs, yet there have been few thorough design studies on how to reduce power in 3D ICs. In this paper, we discuss design methodologies to reduce power consumption in 3D IC designs using a commercial-grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3D ICs, four design techniques are explored: (1) 3D floorplanning, (2) metal layer usage control for intra-block-level routing, (3) dual-Vth design, and (4) functional unit block (FUB) folding. With aforementioned methods combined, our 2-tier 3D designs provide up to 52.3% reduced footprint, 25.5% shorter wirelength, 30.2% decreased buffer cell count, and 21.2% power reduction over the 2D counterpart under the same performance.

Theoretical Analysis of Thermal Conductivity in Amorphous Inter-layer Dielectrics

Understanding thermal conduction in interlayer dielectrics (ILDs) is important for the optimal design of interconnect layers in backend semiconductor processing for future high-performance nano-scale devices. Reduced thermal conductivity of porous ILDs for example can adversely affect the temperature rise in the embedded metal lines leading to un-desirable reliability issues and design constraints. In this paper, we report results of our theoretical and experimental investigation of thermal transport in amorphous and porous dielectrics. A phonon-hopping model has been adapted to calculate the thermal conductivity in disordered materials. The value of hopping integral has been calculated by comparing the modeling results with experimental data for various amorphous and porous materials. The model shows reasonable agreement with experimental data for various amorphous materials including SiO 2 and other glasses over a wide temperature range from 50K – 300K. The model suggests that the hopping of localized high frequency phonons is a dominant thermal transport mechanism in such material systems.