Sarvesh Bhardwaj

Predictive Modeling of the NBTI Effect for Reliable Design

This paper presents a predictive model for the negative bias temperature instability (NBTI) of PMOS under both short term and long term operation. Based on the reaction-diffusion (R-D) mechanism, this model accurately captures the dependence of NBTI on the oxide thickness (tox), the diffusing species (H or H2) and other key transistor and design parameters. In addition, a closed form expression was derived for the threshold voltage change (DeltaVth ) under multiple cycle dynamic operation. Model accuracy and efficiency were verified with 90-nm experimental and simulation data. The impact of NBTI was further investigated on representative digital circuits

The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis

Negative-bias-temperature instability (NBTI) has become the primary limiting factor of circuit life time. In this paper, we develop a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity. Given a circuit topology and input switching activity, we propose an efficient method to predict the degradation of circuit speed over a long period of time. The effectiveness of our method is comprehensively demonstrated with the International Symposium on Circuits and Systems (ISCAS) benchmarks and a 65-nm industrial design. Furthermore, we extract the following key design insights for reliable circuit design under NBTI effect, including: 1) During dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; 2) There is an optimum supply voltage that leads to the minimum of circuit performance degradation; circuit degradation rate actually goes up if supply voltage is lower than the optimum value; 3) Circuit performance degradation due to NBTI is highly sensitive to input vectors. The difference in delay degradation is up to 5× for various static and dynamic operations. Finally, we examine the interaction between NBTI effect, and process and design uncertainty in realistic conditions.

The impact of NBTI on the performance of combinational and sequential circuits

Negative-bias-temperature-instability (NBTI) has become the primary limiting factor of circuit lifetime. In this work, we develop a general framework for analyzing the impact of NBTI on the performance of a circuit, based on various circuit parameters such as the supply voltage, temperature, and node switching activity of the signals etc. We propose an efficient method to predict the degradation of circuit performance based on circuit topology and the switching activity of the signals over long periods of time. We demonstrate our results on ISCAS benchmarks and a 65 nm industrial design. The framework is used to provide key design insights for designing reliable circuits. The key design insights that we obtain are: (1) degradation due to NBTI is most sensitive on the input patterns and the duty cycle; the difference in the delay degradation can be up to 5X for various static and dynamic conditions, (2) during dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; (3) NBTI has marginal impact on the clock signal.

A framework for statistical timing analysis using non-linear delay and slew models

In this paper, we propose a framework for statistical static timing analysis (SSTA) considering intra-die process variations. Given a cell library, we propose an accurate method to characterize the gate and interconnect delay as well as slew as a function of underlying parameter variations. Using these accurate delay models, we propose a method to perform SSTA based on a quadratic delay and slew model. The method is based on efficient dimensionality reduction technique used for accurate computation of the max of two delay expansions. Our results indicate less than 4% error in the variance of the delay models compared to SPICE Monte Carlo and less than 1% error in the variance of the circuit delay compared to Monte Carlo simulations

Leakage minimization of nano-scale circuits in the presence of systematic and random variations

This paper presents a novel gate sizing methodology to minimize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The existing statistical leakage model of Rao et al. (2004) is extended to include the variations in gate sizes as well as systematic variations. We propose techniques to efficiently evaluate constraints on the /spl alpha/-percentile of the path delays without enumerating the paths in the circuit. The complexity of evaluating the objective function is O(|N|/sup 2/) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with |N| gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution.

Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits

This paper proposes the use of Karhunen-Loeve expansion (KLE) for accurate and efficient modeling of intra-die correlations in the semiconductor manufacturing process. We demonstrate that the KLE provides a significantly more accurate representation, of the underlying stochastic process compared to the traditional approach of dividing the layout into grids and applying principal component analysis (PCA). By comparing the results of leakage analysis using both KLE and the existing approaches, we show that using KLE can provide up to 4-5times reduction in the variability space (number of random variables) while maintaining the same accuracy. We also propose an efficient leakage minimization algorithm that maximizes the leakage yield while satisfying probabilistic constraints on the delay

Secure and Robust Localization in a Wireless Ad Hoc Environment

We study the problem of accurate localization of static or mobile nodes in a wireless ad hoc network using the distance estimates of a group of untrusted anchors within the communication range of the nodes. Some of the anchors may be malicious and may independently lie about the distance estimate. The malicious anchors may also collude to lie about the distance estimates. In both cases, accurate node localization may be seriously undermined. We propose a scheme that performs accurate localization of the nodes in the network despite the presence of such malicious anchors. We also show how to identify most of these malicious anchors. In the case where measurements are error free, we derive a critical threshold B for the number of malicious anchors that can be tolerated in the localization process without undermining accuracy. We also show how to correctly localize a node and identify all the malicious anchors in this setting. In the presence of measurement errors, we propose a convex optimization-based localization scheme that can accurately localize a node, as long as the number of malicious anchors in its communication range is no more than B. Simulation results show that our schemes are very effective. When the measurements are error prone and the number of malicious anchors is no more than B , our scheme localizes a node with an error less than 8% and is also able to identify a significant number of malicious anchors. Our schemes guarantee that a true anchor is not identified as malicious.

Scalable model for predicting the effect of negative bias temperature instability for reliable design

The authors present a predictive model for the negative bias temperature instability (NBTI) of PMOS under both short term and long term operation. On the basis of the reaction–diffusion mechanism, this model accurately captures the dependence of NBTI on the oxide thickness (tox), the diffusing species (H or H2) and other key transistor and design parameters. In addition, a closed form expression for the threshold voltage change (ΔVth) under multiple cycle dynamic operation is derived. Model accuracy and efficiency were verified with 180, 130 and 90 nm silicon data. The impact of NBTI on the delay degradation of a ring oscillator and the various metrics of the SRAM such as its data retention voltage, read and hold margins, as well as read and write delay, is also investigated.

A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations

In this paper, we present a unified approach for the statistical timing and leakage analysis of circuits in the presence of intradie variations. The intradie variations in device parameters are modeled as a spatial stochastic process with a given covariance function. The covariance function is used to construct a Karhunen-Loeve expansion of the spatial process. This leads to representing the various parameters of all components on the chip in terms of a common set of abstract random variables. The leakage and propagation delay of each gate are represented as quadratic polynomials (QPs), which are elements of a vector space whose bases are multivariate quadratic orthogonal polynomials of the device parameters. In the case of signal arrival times, we describe an efficient method to propagate the QPs through the circuit to obtain a QP representation of the signal arrival times at the primary outputs. The analysis is extended to include sequential components so that flip-flop parameters and clock arrival times can be treated as random variables. This allows efficient estimation of the timing yield of the circuit. We show how a similar representation of QP can be used to model leakage of gates and develop an efficient method to compute a QP representation of the total chip leakage. The proposed techniques and quadratic models were exercised on ISCAS89 benchmark circuits and compared with Monte Carlo (MC) simulations. The results show that the techniques are very accurate and several orders of magnitude faster than MC simulation.

Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage

This paper proposes a novel methodology for statistical leakage minimization of digital circuits. A function of mean and variance of the circuit leakage is minimized with constraint on a-percentile of the delay using physical delay models. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables can provide significant amount of power savings. The leakage minimization problem is formulated as a multivariable convex optimization problem. We demonstrate that statistical optimization can lead to more than 37% savings in nominal leakage compared to worst-case techniques that perform only gate sizing