Praveen Ghanta

Stochastic analysis of interconnect performance in the presence of process variations

Deformations in interconnect due to process variations can lead to significant performance degradation in deep sub-micron circuits. Timing analyzers attempt to capture the effects of variation on delay with simplified models. The timing verification of RC or RLC networks requires the substitution of such simplified models with spatial stochastic processes that capture the random nature of process variations. The present work proposes a new and viable method to compute the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by using the Galerkin approach of minimizing the Hilbert space norm of the residual error. The key advance of the proposed method is that it provides a functional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called OPERA, results from OPERA simulations on commercial design test cases match well with those from the classical Monte Carlo SPICE simulations and from perturbation methods. Additionally OPERA shows good computational efficiency: speedup factor of 60 has been observed over Monte Carlo SPICE simulations.

Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations

Variations in the interconnect geometry of nanoscale ICs translate to variations in their performance. The resulting diminished accuracy in the estimates of performance at the design stage can lead to a significant reduction in the parametric yield. Thus, determining an accurate statistical description (e.g., moments, distribution, etc.) of the interconnects response is critical for designers. In the presence of significant variations, device or interconnect model parameters such as wire resistance, capacitance, etc., need to modeled as random variables or as spatial random processes. The corner-based analysis is not accurate, and simulations based on sampling require long computation times due to the large number of parameters or random variables. This study proposes an efficient method of computing the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by projecting the infinite series representation onto a finite dimensional subspace. The advantage of the proposed method is that it provides a functional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called orthogonal polynomial expansions for response analysis (OPERA). Results from OPERA simulations on a number of design test cases match well with those from the classical Monte Carlo simulation program with integrated circuits emphasis (SPICE) and from perturbation methods. Additionally, OPERA shows good computational efficiency: speedup of up to two orders of magnitude have been observed over Monte Carlo SPICE simulations

Stochastic Power Grid Analysis Considering Process Variations

In this paper, we investigate the impact of interconnect and device process variations on voltage fluctuations in power grids. We consider random variations in the power grids electrical parameters as spatial stochastic processes and propose a new and efficient method to compute the stochastic voltage response of the power grid. Our approach provides an explicit analytical representation of the stochastic voltage response using orthogonal polynomials in a Hilbert space. The approach has been implemented in a prototype software called OPERA (Orthogonal Polynomial Expansions for Response Analysis). Use of OPERA on industrial power grids demonstrated speed-ups of up to two orders of magnitude. The results also show a significant variation of about /spl plusmn/35% in the nominal voltage drops at various nodes of the power grids and demonstrate the need for variation-aware power grid analysis.

A framework for statistical timing analysis using non-linear delay and slew models

In this paper, we propose a framework for statistical static timing analysis (SSTA) considering intra-die process variations. Given a cell library, we propose an accurate method to characterize the gate and interconnect delay as well as slew as a function of underlying parameter variations. Using these accurate delay models, we propose a method to perform SSTA based on a quadratic delay and slew model. The method is based on efficient dimensionality reduction technique used for accurate computation of the max of two delay expansions. Our results indicate less than 4% error in the variance of the delay models compared to SPICE Monte Carlo and less than 1% error in the variance of the circuit delay compared to Monte Carlo simulations

Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits

This paper proposes the use of Karhunen-Loeve expansion (KLE) for accurate and efficient modeling of intra-die correlations in the semiconductor manufacturing process. We demonstrate that the KLE provides a significantly more accurate representation, of the underlying stochastic process compared to the traditional approach of dividing the layout into grids and applying principal component analysis (PCA). By comparing the results of leakage analysis using both KLE and the existing approaches, we show that using KLE can provide up to 4-5times reduction in the variability space (number of random variables) while maintaining the same accuracy. We also propose an efficient leakage minimization algorithm that maximizes the leakage yield while satisfying probabilistic constraints on the delay

Stochastic variational analysis of large power grids considering intra-die correlations

For statistical timing and power analysis that are very important problems in the sub-100 nm technologies, stochastic analysis of power grids that characterizes the voltage fluctuations due to process variations is inevitable. In this paper, we propose an efficient algorithm for the variational analysis of large power grids in the presence of a significant number of Gaussian intra-die process variables that are correlated. We consider variations in the power grids electrical parameters as spatial stochastic processes and express them as linear expansions in an orthonormal series of random variables using the Karhunen-Loeve (KLE) method. The voltage response is then represented as an orthonormal polynomial series and the coefficients are obtained optimally using the Galerkin method. We propose a novel method to separate the stochastic analysis for the random variables that effect only the inputs (e.g, drain currents) and for those that effect the system parameters as well (e.g., conductance, capacitance). We show that this parallelism can result in significant speed-ups in addition to the speed-ups inherent to Galerkin-based methods. Our analysis has been applied to several industrial power grids and the results show speed-ups of up to two orders of magnitude over Monte Carlo simulations for comparable accuracy

Variational Interconnect Delay Metrics for Statistical Timing Analysis

For statistical timing analysis and physical design optimization, interconnect delay metrics that model the delay as a function of the metal process variations are very important. Accurate linear or at most second order delay models in terms of the process variables are necessary to efficiently propagate uncertainty in the state-of-the-art VLSI designs with millions of transistors and on chip interconnects. In this paper, we develop a method to extend the traditional moment based delay analysis of interconnects to consider the impact of Gaussian metal process variations and obtain mean-square optimal linear delay models for interconnects. We consider linear models for the variations in the conductance and capacitance of interconnects and represent the moments (m0, m1, m2) of the interconnect impulse response as a first order orthogonal polynomial series expansion in the process variables. We obtain the coefficients of the expansion by using the Galerkin residual error minimization method on the recursive equations that relate the interconnect moments (m0, m1 , m2). We compare the accuracy of our approach against SPICE based Monte Carlo simulations and demonstrate a good match

A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations

Integrated circuits today rely on extensive re-use of pre-characterized IP bocks and macro cells to meet the demand for high performance system on chip (SoC). In this paper we propose a methodology for characterization of IP blocks and macro cells for statistical timing analysis considering process variations and spatial correlations. We develop efficient models for capturing both inter-die and intra-die variations in devices and interconnects. Increasing variability of the process parameters in sub-nanometer designs requires instance-specific characterization of these design blocks. We propose a technique for instance- specific calibration of pre-characterized timing model. The proposed approach was evaluated on large industrial designs of 1.2 M and 3.5 M gates in 65 nm technology and validated against SPICE for accuracy.

Analysis of Power Supply Noise in the Presence of Process Variations

Characterizing the impact of variability on circuit performance measurements (delay, power, and signal integrity) is necessary to avoid chip failure. The authors present a comprehensive methodology for analyzing the impact of device and metal variations on the power supply noise, and hence the signal integrity, of on-chip power grids.

Analytical expressions for phase noise eigenfunctions of LC oscillators

We obtain analytical expressions for eigenfunctions that characterize the phase noise performance of generic LC oscillator structures. Using these, we also obtain analytical expressions for the timing jitter and spectrum of such oscillators. Our approach is based on identifying three fundamental parameters, derived from the oscillators steady state, that characterize these eigenfunctions. Our analysis accounts for the nonlinear mechanism that stabilizes oscillator amplitudes. It also lays out, quantitatively and in analytical form, how symmetry in an LC oscillators negative resistance mechanism impacts the oscillators eigenfunctions and its phase noise/jitter characteristics. We show that symmetry results in particularly simple forms for the PPV and resultant phase noise. We compare our expressions with existing LC oscillator design formulae and show that the expressions match for symmetric nonlinearities. We validate our analytical results against simulation on practical CMOS LC oscillator circuits. Our expressions and symmetry results are expected to be useful tools for optimizing phase noise performance during the design of LC oscillators.