Sasikumar Cherubal

Prediction of analog performance parameters using fast transient testing

In this paper, a fast transient testing methodology for predicting the performance parameters of analog circuits is presented. A transient test signal is applied to the circuit under (cut) test and the transient response of the circuit is sampled and analyzed to predict the circuits performance parameters. An algorithm for generating the optimum transient test signal is presented. The methodology is demonstrated in a production environment using a low-power opamp. Result from production test data showed: 1) a ten times speedup in production testing; 2) accurate prediction of the performance parameters; and 3) a simpler test configuration.

Hierarchical specification-driven analog fault modeling for efficient fault simulation and diagnosis

In this paper we discuss the capabilities of the MiST PROFIT (Mixed Signal Test Program for Fault Insertion and Testing) software for hierarchical fault modeling, tolerance modeling, fault clustering and fault diagnosis of complex mixed-signal systems. The software is designed to exploit the relationships between high level system specifications and module-level faults in complex and nonlinear mixed signal systems. Hierarchical simulation based methods are used to capture fault effects at different levels of circuit abstraction. The key features of our approach are: (a) the ability to compute tolerance effects from nonlinear behavioral models at different levels of circuit design hierarchy accurately using low-cost simulation based methods, (b) the ability to perform compaction of fault effects while transferring fault effects from the leaf cells to the highest level behavioral models, (c) the ability to capture parametric (soft) failure effects over the entire anticipated range of faulty parameter values and (d) the ability to construct fault dictionaries given a set of least replaceable units to diagnose.

Parametric fault diagnosis for analog systems using functional mapping

We propose a new Simulation-After-Test (SAT) methodology for accurate diagnosis of circuit parameters in large analog circuits. Our methodology is based on constructing a non-linear regression model using prior circuit simulation, which relates a set of measurements to the circuits internal parameters. First, we give algorithms to select measurements that give all the diagnostic information about the Circuit-Under-Test (CUT). From these selected measurements, we solve for the internal parameters of the circuit using iterative numerical techniques. The methodology has been applied to several mixed-signal test benchmark circuits and has applications in process debugging for mixed-signal integrated circuits (ICs) as well troubleshooting and repair of board level systems.

A high-resolution jitter measurement technique using ADC sampling

In this paper, we propose a new technique for jitter measurement that can be implemented using commercially available, off-the-shelf components. The technique implements a high-resolution, high-speed, phase detector using a high-speed Analog-to-Digital Converter (ADC). The technique is shown to have high resolution and low test time compared to currently available techniques. Experimental results to demonstrate the effectiveness of the technique are presented.

Concurrent RF test using optimized modulated RF stimuli

With proliferation in wireless applications, RF circuitry is being included in a large number of Integrated Circuit (IC) designs. The testing of RF devices has become increasingly expensive due to the high cost of RF testers as well as the test times for RF circuits. The use of a new concurrent test methodology reduces RF test time by measuring multiple RF parameters in parallel using modulated RF stimuli. Experimental results on a GaAs Low-Noise Amplifier (LNA) are described.

Optimal linearity testing of analog-to-digital converters using a linear model

To maintain an acceptable level of quality in the production of analog-to-digital converters (ADCs), the linearity metrics of every ADC has to be measured and checked against performance specification limits. As ADCs continue to improve in resolution, their testing has becoming increasingly demanding in terms of test time. In this paper, we demonstrate a technique for reducing the test time for ADCs. The technique is shown to be significantly better than currently available techniques and can be easily integrated into current production test methodologies. Experimental results in simulation and on actual hardware are shown to demonstrate the technique.

Production deployment of a fast transient testing methodology for analog circuits: case study and results

This paper describes the production deployment of a fast transient testing (FASTest) methodology for analog circuits. Unlike traditional sequential speciJication testing applied to analog circuits today, the FASTest transient test methodology applies optimized and concise transient stimuli to multiple pins of an IC simultaneously. The resulting response is captured, and transformed using algorithms into standard IC test parameters. The test process is transparent to the test engineer who only sees the same test results that would have been obtained with (current) standard speciJication testing of analog ICs. Implementation of the transient test methodology and results from a large volume qualification procedure for a precision operational ampli

Fault diagnosis for mixed-signal electronic systems

er are described. In production test, the FASTest test methodology is seen to provide more than 3 1 reduction in test time, while providing the same test quality.

Optimal INL/DNL testing of A/D converters using a linear model

In this paper, we propose an efficient methodology to diagnose faults in complex mixed-signal systems. The proposed technique combines the advantages of simulation-before-test and simulation-after-test approaches. Given a faulty circuit, a hierarchical fault dictionary (a list of all faulty behaviors of the circuit, used for fault location) is used to locate the faulty component. The computational requirements during fault dictionary construction are minimized by hierarchical fault clustering and behavioral fault modeling. The resulting fault dictionary is most compact in size and contains complete diagnostic accuracy. Once the faulty component is identified, a novel parameter identification algorithm determines the values of the parameters corresponding to the faulty component. The proposed approach minimizes the off-line computation required by a fault dictionary technique as well as the online computation that is typical of a simulation-after-test technique. It is also robust to component tolerances and measurement inaccuracies, as the precise values of the parameters are determined. Finally, the proposed fault diagnosis technique can diagnose a faulty component at any level of design hierarchy, or identify the exact value of the faulty parameters, according to the intended resolution of diagnosis.

DIBPro: Automatic Diagnostic Program Generation Tool

As Analog to Digital Converters continue to improve in resolution, their linearity testing has become increasingly challenging in terms of test accuracy and test time. In this paper we present a technique for estimation the linearity metrics of an ADC that is optimal in terms of expected r.m.s error in INL/DNL estimates, for a given test time. Experimental results measured on an ADC from industry to validate the effectiveness of the technique are presented.