Pramodchandran N. Variyam

Prediction of analog performance parameters using fast transient testing

In this paper, a fast transient testing methodology for predicting the performance parameters of analog circuits is presented. A transient test signal is applied to the circuit under (cut) test and the transient response of the circuit is sampled and analyzed to predict the circuits performance parameters. An algorithm for generating the optimum transient test signal is presented. The methodology is demonstrated in a production environment using a low-power opamp. Result from production test data showed: 1) a ten times speedup in production testing; 2) accurate prediction of the performance parameters; and 3) a simpler test configuration.

Specification-driven test generation for analog circuits

In this paper, a new methodology for generating transient tests to detect faults in analog circuits is presented. Relationship between circuit functionalities and physical failures is exploited to derive these tests. These fast transient tests can be used for implicitly verifying the circuit specifications. A fast fault simulation algorithm for linear analog circuits based on state-space representation and adjoint network method is also presented. This fault simulation algorithm is used for generating transient test for linear analog circuits. For nonlinear circuits, an existing circuit simulator is used for test generation. The generated tests are evaluated and found to give low misclassification rates for a large class of analog circuits.

Increasing the IDDQ test resolution using current prediction

The Variations in IDDQ due to process disturbances for sub-micron ICs is comparable to magnitude of defect induced currents. This is making traditional IDDQ testing ineffective in detecting defects in sub-micron ICs. This paper presents a methodology called current prediction for enhancing the effectiveness of IDDQ testing. In the proposed methodology, a set of IDDQ measurements are performed on the device and the value of each IDDQ current are predicted using regression models. Absolute value of the difference between measured and predicted IDDQ (residuals of current prediction) are used for identifying defective devices. The residuals of current prediction are very sensitive to the defect currents and is insensitive to process variations thus increasing the IDDQ test resolution. This technique is compared with traditional and delta IDDQ testing techniques using the production test data from two different ICs. Results show that considerable improvement in the IDDQ test quality can be achieved with the proposed technique.

Digital-compatible BIST for analog circuits using transient response sampling

For complex mixed-signal designs, BIST is becoming a necessity. The BIST scheme presented here maximizes coverage of parametric and catastrophic failures and provides an all-digital BIST solution to analog circuits.

Accurate measurement of multi-tone power ratio (MTPR) of ADSL devices using low cost testers

Measurement of multi-tone power ratio (MTPR) on the transmitter output of a central office ADSL analog front-end device (AFE) poses stringent requirements on the linearity of the ATE digitizer. Cost of the ATE digitizer that can perform this test in a specification compliant manner is prohibitively high. In this paper, a test technique to perform TX MTPR test on a central office ADSL device using low-cost automatic test equipment (ATE) is proposed. The proposed technique is based on adding optimum dither noise to the output of the DUT, to improve the performance of the low cost ATE digitizer. The dither reduces the distortion caused by the static errors in the ATE digitizer by randomizing these nonlinear errors. Results obtained using the proposed method on ASDL AFE devices show an improvement of /spl sim/7dB in MTPR measurement with very good repeatability.

Measuring code edges of ADCs using interpolation and its application to offset and gain error testing

Measuring analog threshold voltage between two different digital codes is a common test performed during production testing of ADCs. Due to the noisy nature of analog signals, this test can take considerable amount of costly test time. This paper presents a fast algorithm for measuring code edges of ADCs. In this method, a gaussian distribution is assumed for noise in ADCs and the code edges are determined by interpolating the inverse cumulative distribution of the gaussian function. A fast testing method for guaranteeing the specifications on offset and gain error is developed as a corollary to the code edge measuring technique. Practical issues in implementing this technique in production testing are discussed. Production test results show excellent repeatability and large saving in production test time.