Sathyanarayanan Raghavan

Magnetic Alignment of Hexagonal Boron Nitride Platelets in Polymer Matrix: Toward High Performance Anisotropic Polymer Composites for Electronic Encapsulation

We report magnetic alignment of hexagonal boron nitride (hBN) platelets and the outstanding material properties of its polymer composite. The magnetically responsive hBN is produced by surface modification of iron oxide, and their orientations can be controlled by applying an external magnetic field during polymer curing. Owing to the anisotropic properties of hBN, the epoxy composite with aligned hBN platelets shows interesting properties along the alignment direction, including significantly reduced coefficient of thermal expansion, reaching ∼28.7 ppm/°C, and enhanced thermal conductivity, 104% higher than that of unaligned counterpart, both of which are observed at a low filler loading of 20 wt %. Our modeling suggests the filler alignment is the major reason for these intriguing material properties. Finite element analysis reveals promising applications for the magnetically aligned hBN-based composites in modern microelectronic packaging.

Study of Chip–Package Interaction Parameters on Interlayer Dielectric Crack Propagation

To meet the electrical performance requirements, copper traces with ultralow- k (ULK) interlayer dielectric (ILD) materials are used in todays semiconductor devices. The dielectric constant (k) of these materials is often reduced through the introduction of pores or inclusions, and thus, the ULK ILD materials have low fracture strength. During flip-chip assembly, thermally induced stresses occurring due to the differential displacement between the substrate and the die can result either in ILD cracking or in ILD delamination in the vicinity of solder bump. Such reliability problems are a cause for concern in semiconductor devices. In this paper, we study such dielectric cracking through numerical models and experiments and present methods to reduce such dielectric cracking. This work uses a finite-element-based submodeling approach to study ILD cracking in flip-chip assemblies. The developed “global” model accounts for the die, the passivation layer, the die pad, the solder bump, the substrate pad, and various layers in the substrate, including the trace pattern effective directional modulus. The displacement boundary conditions from the global model under flip-chip assembly cooling are then applied to a “local model,” which accounts for the die with its backend-of-line (BEOL) stack details, such as the die pad, the passivation layer, the solder bump, the substrate pad, and layers in the substrate. The local model focuses on the most critical solder bump, based on global stress contours. Next, cohesive cracks are introduced at various locations in the ULK layers above the critical solder bump and are allowed to propagate under flip-chip assembly reflow thermal conditions. It can be seen that the elastic energy available for crack propagation initially increases with crack length, but then starts to decay, indicating that the ILD cracking is often confined in the vicinity of one bump. Furthermore, the results from the models have been compared against experimental failure analysis results of 45-nm (C45) devices. It is also shown that the models can provide geometry and material guidelines to reduce ILD cracking.

Interlayer dielectric cracking in back end of line (BEOL) stack

Copper/low-k dielectrics are used in todays ICs to enhance electrical performance. The low-k interlayer dielectric (ILD) materials have low fracture strength due to the presence of pores or other inclusions to reduce the dielectric constant. During flip-chip assembly, when the die/substrate structure is cooled down from reflow temperature to room temperature, thermo-mechanical strains and stresses develop in the solder bumps. These thermally-induced stresses are due to the differential displacement between the substrate and the die as a result of coefficient of thermal expansion (CTE) mismatch between the die and the substrate. When the thermo-mechanical stresses are high, they can result either in ILD cracking or in ILD delamination in the vicinity of solder bump. This ILD fractures are circular in shape and appear as a white spot in C-mode scanning acoustic microscopy (CSAM) images, and thus, they are often referred to as “white bumps.” In this paper, we present a finite-element-based sub-modeling approach to study the ILD cracking in flip-chip assemblies. The developed “global” model accounts for the die, passivation layer, die pad, solder bump, substrate pad, and various layers in the substrate including the trace-pattern effective directional modulus. The displacement boundary conditions from the global model under flip-chip assembly cooling are then applied to a “local model” which accounts for the die with its back-end-of-line (BEOL) stack, die pad, passivation layer, solder bump, substrate pad, and layers in the substrate. The local model focuses on the most critical solder bump, based on global stress contours. Next, cohesive and interfacial cracks are introduced in the ULK layers present in the BEOL stack, and the energy available for cohesive crack and interfacial crack propagation has been determined. It can be seen that energy available for crack propagation initially increases with crack length, but the energy starts to decay after a particular crack length indicating that the ILD cracking is often confined in the vicinity of one bump. The models can also provide valuable insight into ILD cracking for a wide range of geometry and material parameters. The results from the models have been compared against available experimental cohesive as well as interfacial fracture toughness data for Cu/dielectric material systems.

Experiments for Obtaining Cohesive-Zone Parameters for Copper-Mold Compound Interfacial Delamination

Interfacial delamination due to mismatch of coefficient of thermal expansion is a prominent failure mechanism of multilayer microelectronic packaging. Current methods for investigating and preventing interfacial delamination rely heavily on interfacial fracture mechanics. Such techniques are effective but also limited because they rely on assumptions about existing cracked geometry. Cohesive-zone modeling is an alternative technique for modeling interfacial delamination that is capable of simulating both crack initiation and crack propagation. This paper presents a methodology for developing a cohesive-zone model for an interface between the copper leadframe and the epoxy molding compound (EMC). Through experiments, the interfacial strength is characterized quantitatively, and load versus displacement data are collected for each experiment. By mimicking these results with a cohesive-zone model, mixed-mode cohesive-zone parameters are obtained. The fully defined mixed-mode cohesive-zone model can be used to simulate interfacial delamination between the copper leadframe and the EMC in any microelectronic package that contains such an interface. Furthermore, the procedure demonstrated here may be employed to characterize a cohesive-zone model for other interfaces in microelectronic packages.

Cohesive zone experiments for copper/mold compound delamination

As complex multi-layered packaging becomes more common in microelectronic design, delamination remains a prominent failure mechanism due to coefficient of thermal expansion mismatch. Numerous studies have investigated interfacial cracking in microelectronic packages. These studies commonly use classical interfacial fracture mechanics analyses, but such analyses require knowledge of starter crack size, locations, and propagation paths. Cohesive zone theory has been identified as an alternative method for modeling crack propagation and delamination without the need for a pre-existing crack. This paper presents a framework to determine mixed-mode cohesive zone parameters using experimental methods. We demonstrate this method by characterizing cohesive zone parameters for a copper/epoxy molding compound interface. Fully characterized cohesive zone elements can be placed at interfaces in finite-element models of microelectronic systems to simulate loading and failure in mixed-mode conditions.

Methodology to Predict Substrate Warpage and Different Techniques to Achieve Substrate Warpage Targets

With the continued demand for fine features, enhanced assembly yield, and improved reliability in the microelectronic packaging industry, there is a need to reduce substrate warpage. Factors such as coefficient of thermal expansion mismatch among several materials in the packaging substrate, modulus of different materials, thickness of different layers, orientation of features in each layer, thermal and mechanical loading conditions influence the substrate warpage, and any effort to reduce substrate warpage needs to address one or more of these factors. One technique to reduce warpage will be through the viscoelastic relaxation of the dielectric material, when other factors cannot be changed for performance, processing, or cost reasons. Thus, it is important to accurately model the viscoelastic relaxation of the dielectric material, and study how the warpage can be reduced either by changing dwell times at different temperatures and/or by introducing appropriate mechanical loads in combination with thermal loads. In this paper, we present two approaches to reduce substrate warpage: 1) by modifying the temperature-time profile of the sequential processing steps, and 2) by using an external mold to reduce the substrate warpage. Based on the simulation results, it appears that significant warpage reduction is achievable through the proposed techniques.

Chip Package Co-Design: Effect of Substrate Warpage on BEOL Reliability

Large-scale integration at lower cost has led to the usage of multi-layered organic substrates in flip-chip assemblies. However, the warpage of substrate plays an important role in the reliability of back-end-of-line (BEOL) stack on a chip. In this work, we study the effect of substrate layer configuration, and thus the warpage of the substrate at reflow temperature on BEOL reliability. A plane-strain flip-chip on substrate assembly model is utilized to study the die and solder stresses for different substrate layer configurations. Apart from studying the die stresses, fracture mechanics based approach is used to study the effect of substrate configuration on energy available for a crack present in back-end-of-line (BEOL) stack. In this paper, we describe the methodology to model the substrate with initial warpage at reflow temperature, characterize the effect of the initial warpage at reflow temperature on die stresses at room temperature and further use fracture mechanics based approach to predict the change in risk for a crack present in BEOL stack for different substrate warpage configurations at reflow temperature.Copyright

Cohesive Zone Models to Predict Multiple White Bumps in Flip-Chip Assemblies

The drive towards increased functional integration and improved performance in microelectronic devices has led to the introduction of more layers and porous dielectric materials in back end of line (BEOL) stack. These materials have low mechanical strength as well as adhesive strength and thus, interfacial delamination is a major reliability concern for modern microelectronic devices. In this work, we present a cohesive zone element based finite-element model to predict failures observed at the end of flip-chip assembly reflow process. During lead-free flip-chip assembly, thermo-mechanical stresses arise due to the coefficient of thermal expansion (CTE) mismatch between the organic substrate and the silicon die. Such stresses can be high enough to cause cracking of interlayer dielectric layers present in the vicinity of solder bump. In order to predict such failures, mixed mode cohesive zone parameters are first extracted from interfacial fracture characterization experiments of real-life BEOL stacks. Then, the characterized cohesive zone elements are embedded in 2D finite-element models of flip-chip assembly to predict the failure region. The predicted failure region is compared against 2D fracture mechanics based models as well as failure analysis experiment results. Cohesive zone elements are then implemented over multiple bumps to examine simultaneous failure of multiple bumps under reflow assembly, and thus, the effectiveness of cohesive zone elements compared to fracture mechanics approach is demonstrated.Copyright

An Efficient Implementation of Polymer Viscoelastic Behavior Through a Pseudo Viscoelastic Model

Modeling of viscoelastic relaxation of polymer materials is important to understand the thermo-mechanical behavior of organic microelectronic systems. However, incorporation of viscoelastic behavior into numerical models makes the models compute-intensive. This paper presents a different technique to incorporate the polymer viscoelastic behavior into the numerical models such that the computation time is not adversely affected without compromising the accuracy of the results obtained. In the proposed “pseudo viscoelastic” modeling technique, the modulus of the viscoelastic material is computed as a function of time and temperature loading history outside of the finite-element simulation, and is then input into the simulation as a thermo-elastic material incorporating the viscoelastic relaxation of the material. This paper compares the warpage results obtained through the proposed technique against a complete viscoelastic simulation model and experimental data, and it is seen that the maximum warpage predi...