George R. Leal

The Redistributed Chip Package: A Breakthrough for Advanced Packaging

The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current wirebond BGA and flip chip BGA packaging. Devices are encapsulated into panels while routing of signals, power, and ground is built directly on the panel. The RCP panel and signal build-up lowers the cost of the package by eliminating wafer bumping and substrates thereby enabling large scale assembly in panel form. The build-up provides better routing capabilities and better integration. Also, by eliminating bumping, the device interconnect is inherently Pb-free, and the stress of the package is reduced enabling ultra-low K device compatibility. The panel is created by attaching device active side down to a substrate, encapsulating and curing the devices, grinding to desired thickness, and then removing the substrate. Signal, power, and ground planes are created using redistribution-like processing. Multi-layer metal RCP packages have passed -40 to 125C air-to-air thermal cycling and HAST after MSL3/260 preconditioning.

Advanced Packaging: The Redistributed Chip Package

The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current wirebond ball grid array (BGA) and flip chip BGA packaging. Devices are encapsulated into panels while routing of signals, power, and ground is built directly on the panel. The RCP panel and signal build up lowers the cost of the package by eliminating wafer bumping and substrates thereby enabling large scale assembly in panel form. The build up provides better routing capabilities and better integration. Also, by eliminating bumping, the device interconnect is inherently Pb-free, and the stress of the package is reduced enabling ultra-low-k device compatibility. The panel is created by attaching the device active side down to a substrate, encapsulating and curing the devices, grinding to desired thickness, and then removing the substrate. Signal, power, and ground planes are created using redistribution-like processing. Multilayer metal RCP packages have passed 40 to 125 C air-to-air thermal cycling and HAST after MSL3/260 preconditioning.

Study of Chip–Package Interaction Parameters on Interlayer Dielectric Crack Propagation

To meet the electrical performance requirements, copper traces with ultralow- k (ULK) interlayer dielectric (ILD) materials are used in todays semiconductor devices. The dielectric constant (k) of these materials is often reduced through the introduction of pores or inclusions, and thus, the ULK ILD materials have low fracture strength. During flip-chip assembly, thermally induced stresses occurring due to the differential displacement between the substrate and the die can result either in ILD cracking or in ILD delamination in the vicinity of solder bump. Such reliability problems are a cause for concern in semiconductor devices. In this paper, we study such dielectric cracking through numerical models and experiments and present methods to reduce such dielectric cracking. This work uses a finite-element-based submodeling approach to study ILD cracking in flip-chip assemblies. The developed “global” model accounts for the die, the passivation layer, the die pad, the solder bump, the substrate pad, and various layers in the substrate, including the trace pattern effective directional modulus. The displacement boundary conditions from the global model under flip-chip assembly cooling are then applied to a “local model,” which accounts for the die with its backend-of-line (BEOL) stack details, such as the die pad, the passivation layer, the solder bump, the substrate pad, and layers in the substrate. The local model focuses on the most critical solder bump, based on global stress contours. Next, cohesive cracks are introduced at various locations in the ULK layers above the critical solder bump and are allowed to propagate under flip-chip assembly reflow thermal conditions. It can be seen that the elastic energy available for crack propagation initially increases with crack length, but then starts to decay, indicating that the ILD cracking is often confined in the vicinity of one bump. Furthermore, the results from the models have been compared against experimental failure analysis results of 45-nm (C45) devices. It is also shown that the models can provide geometry and material guidelines to reduce ILD cracking.

Implementation of a mobile phone module with redistributed chip packaging

The redistributed chip packaging is an embedded chip technology that eliminates the need for wirebonds and flip chip bumps. This technology enables smaller packages at a lower cost, while providing improved mechanical, electrical and thermal performance. The process involves producing panels placing the chip active face down along with an embedded ground plane (EGP) and screen printing encapsulant to embed the die. Subsequently alternate layers of dielectric and Cu metallization are built up and the packages are sawn into individual units. The use of wafer fabrication tools enables finer lines and spaces in the build-up layers. This paper will discuss process conditions during the panelization and the integration of the base function of an i.275 GSM/EDGE mobile phone into a single module measuring a maximum of 1 square inch. The design of the EGP and the role of simulations to achieve a robust, reliable package will also be discussed. The outputs included moisture sensitivity level (MSL) 3 testing, air-to-air thermal cycling (- 40C/125C) and unbiased highly accelerated stress testing (HAST). Testing of RCP packages will also be discussed.

Chip Package Co-Design: Effect of Substrate Warpage on BEOL Reliability

Large-scale integration at lower cost has led to the usage of multi-layered organic substrates in flip-chip assemblies. However, the warpage of substrate plays an important role in the reliability of back-end-of-line (BEOL) stack on a chip. In this work, we study the effect of substrate layer configuration, and thus the warpage of the substrate at reflow temperature on BEOL reliability. A plane-strain flip-chip on substrate assembly model is utilized to study the die and solder stresses for different substrate layer configurations. Apart from studying the die stresses, fracture mechanics based approach is used to study the effect of substrate configuration on energy available for a crack present in back-end-of-line (BEOL) stack. In this paper, we describe the methodology to model the substrate with initial warpage at reflow temperature, characterize the effect of the initial warpage at reflow temperature on die stresses at room temperature and further use fracture mechanics based approach to predict the change in risk for a crack present in BEOL stack for different substrate warpage configurations at reflow temperature.Copyright

Cohesive Zone Models to Predict Multiple White Bumps in Flip-Chip Assemblies

The drive towards increased functional integration and improved performance in microelectronic devices has led to the introduction of more layers and porous dielectric materials in back end of line (BEOL) stack. These materials have low mechanical strength as well as adhesive strength and thus, interfacial delamination is a major reliability concern for modern microelectronic devices. In this work, we present a cohesive zone element based finite-element model to predict failures observed at the end of flip-chip assembly reflow process. During lead-free flip-chip assembly, thermo-mechanical stresses arise due to the coefficient of thermal expansion (CTE) mismatch between the organic substrate and the silicon die. Such stresses can be high enough to cause cracking of interlayer dielectric layers present in the vicinity of solder bump. In order to predict such failures, mixed mode cohesive zone parameters are first extracted from interfacial fracture characterization experiments of real-life BEOL stacks. Then, the characterized cohesive zone elements are embedded in 2D finite-element models of flip-chip assembly to predict the failure region. The predicted failure region is compared against 2D fracture mechanics based models as well as failure analysis experiment results. Cohesive zone elements are then implemented over multiple bumps to examine simultaneous failure of multiple bumps under reflow assembly, and thus, the effectiveness of cohesive zone elements compared to fracture mechanics approach is demonstrated.Copyright